2 * Copyright (c) 2007 MIPS Technologies, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Korey Sewell
34 #include "cpu/inorder/resources/execution_unit.hh"
35 #include "cpu/inorder/resource_pool.hh"
36 #include "cpu/inorder/cpu.hh"
39 using namespace ThePipeline
;
41 ExecutionUnit::ExecutionUnit(string res_name
, int res_id
, int res_width
,
42 int res_latency
, InOrderCPU
*_cpu
, ThePipeline::Params
*params
)
43 : Resource(res_name
, res_id
, res_width
, res_latency
, _cpu
)
47 ExecutionUnit::regStats()
49 predictedTakenIncorrect
50 .name(name() + ".predictedTakenIncorrect")
51 .desc("Number of Branches Incorrectly Predicted As Taken.");
53 predictedNotTakenIncorrect
54 .name(name() + ".predictedNotTakenIncorrect")
55 .desc("Number of Branches Incorrectly Predicted As Not Taken).");
57 lastExecuteCycle
= curTick
;
60 .name(name() + ".executions")
61 .desc("Number of Instructions Executed.");
67 ExecutionUnit::execute(int slot_num
)
69 ResourceRequest
* exec_req
= reqMap
[slot_num
];
70 DynInstPtr inst
= reqMap
[slot_num
]->inst
;
71 Fault fault
= reqMap
[slot_num
]->fault
;
72 ThreadID tid
= inst
->readTid();
73 int seq_num
= inst
->seqNum
;
75 exec_req
->fault
= NoFault
;
77 DPRINTF(InOrderExecute
, "[tid:%i] Executing [sn:%i] [PC:%#x] %s.\n",
78 tid
, seq_num
, inst
->readPC(), inst
->instName());
80 switch (exec_req
->cmd
)
84 if (curTick
!= lastExecuteCycle
) {
85 lastExecuteCycle
= curTick
;
89 if (inst
->isMemRef()) {
90 panic("%s not configured to handle memory ops.\n", resName
);
91 } else if (inst
->isControl()) {
93 fault
= inst
->execute();
98 if (fault
== NoFault
) {
99 // If branch is mispredicted, then signal squash
100 // throughout all stages behind the pipeline stage
101 // that got squashed.
102 if (inst
->mispredicted()) {
103 int stage_num
= exec_req
->getStageNum();
104 ThreadID tid
= inst
->readTid();
106 // If it's a branch ...
107 if (inst
->isDirectCtrl()) {
108 assert(!inst
->isIndirectCtrl());
110 if (inst
->predTaken() && inst
->isCondDelaySlot()) {
111 inst
->bdelaySeqNum
= seq_num
;
112 inst
->setPredTarg(inst
->nextPC
);
114 DPRINTF(InOrderExecute
, "[tid:%i]: Conditional branch inst"
115 "[sn:%i] PC %#x mispredicted as taken.\n", tid
,
117 } else if (!inst
->predTaken() && inst
->isCondDelaySlot()) {
118 inst
->bdelaySeqNum
= seq_num
;
119 inst
->setPredTarg(inst
->nextPC
);
120 inst
->procDelaySlotOnMispred
= true;
122 DPRINTF(InOrderExecute
, "[tid:%i]: Conditional branch inst."
123 "[sn:%i] PC %#x mispredicted as not taken.\n", tid
,
126 #if ISA_HAS_DELAY_SLOT
127 inst
->bdelaySeqNum
= seq_num
+ 1;
128 inst
->setPredTarg(inst
->nextNPC
);
130 inst
->bdelaySeqNum
= seq_num
;
131 inst
->setPredTarg(inst
->nextPC
);
133 DPRINTF(InOrderExecute
, "[tid:%i]: Misprediction detected at "
134 "[sn:%i] PC %#x,\n\t squashing after delay slot "
135 "instruction [sn:%i].\n",
136 tid
, seq_num
, inst
->PC
, inst
->bdelaySeqNum
);
137 DPRINTF(InOrderStall
, "STALL: [tid:%i]: Branch "
138 "misprediction at %#x\n", tid
, inst
->PC
);
141 DPRINTF(InOrderExecute
, "[tid:%i] Redirecting fetch to %#x.\n", tid
,
142 inst
->readPredTarg());
144 } else if(inst
->isIndirectCtrl()){
145 #if ISA_HAS_DELAY_SLOT
146 inst
->setPredTarg(inst
->nextNPC
);
147 inst
->bdelaySeqNum
= seq_num
+ 1;
149 inst
->setPredTarg(inst
->nextPC
);
150 inst
->bdelaySeqNum
= seq_num
;
153 DPRINTF(InOrderExecute
, "[tid:%i] Redirecting fetch to %#x.\n", tid
,
154 inst
->readPredTarg());
156 panic("Non-control instruction (%s) mispredicting?!!",
157 inst
->staticInst
->getName());
160 DPRINTF(InOrderExecute
, "[tid:%i] Squashing will start from stage %i.\n",
163 cpu
->pipelineStage
[stage_num
]->squashDueToBranch(inst
, tid
);
165 inst
->squashingStage
= stage_num
;
167 // Squash throughout other resources
168 cpu
->resPool
->scheduleEvent((InOrderCPU::CPUEventType
)ResourcePool::SquashAll
,
171 if (inst
->predTaken()) {
172 predictedTakenIncorrect
++;
174 predictedNotTakenIncorrect
++;
177 DPRINTF(InOrderExecute
, "[tid:%i]: [sn:%i]: Prediction Correct.\n",
178 inst
->readTid(), seq_num
);
183 warn("inst [sn:%i] had a %s fault", seq_num
, fault
->name());
186 // Regular ALU instruction
187 fault
= inst
->execute();
190 if (fault
== NoFault
) {
193 DPRINTF(InOrderExecute
, "[tid:%i]: [sn:%i]: The result of execution is 0x%x.\n",
194 inst
->readTid(), seq_num
, (inst
->resultType(0) == InOrderDynInst::Float
) ?
195 inst
->readFloatResult(0) : inst
->readIntResult(0));
199 warn("inst [sn:%i] had a %s fault", seq_num
, fault
->name());
200 cpu
->trap(fault
, tid
);
207 fatal("Unrecognized command to %s", resName
);