src/cpu/inorder/resources/execution_unit.cc

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #include <vector>
  33 #include <list>
  34 #include "cpu/inorder/resources/execution_unit.hh"
  35 #include "cpu/inorder/resource_pool.hh"
  36 #include "cpu/inorder/cpu.hh"
  37
  38 using namespace std;
  39 using namespace ThePipeline;
  40
  41 ExecutionUnit::ExecutionUnit(string res_name, int res_id, int res_width,
  42                              int res_latency, InOrderCPU *_cpu,
  43                              ThePipeline::Params *params)
  44     : Resource(res_name, res_id, res_width, res_latency, _cpu),
  45       lastExecuteTick(0), lastControlTick(0)
  46 { }
  47
  48 void
  49 ExecutionUnit::regStats()
  50 {
  51     predictedTakenIncorrect
  52         .name(name() + ".predictedTakenIncorrect")
  53         .desc("Number of Branches Incorrectly Predicted As Taken.");
  54
  55     predictedNotTakenIncorrect
  56         .name(name() + ".predictedNotTakenIncorrect")
  57         .desc("Number of Branches Incorrectly Predicted As Not Taken).");
  58
  59     executions
  60         .name(name() + ".executions")
  61         .desc("Number of Instructions Executed.");
  62
  63
  64     predictedIncorrect
  65         .name(name() + ".mispredicted")
  66         .desc("Number of Branches Incorrectly Predicted");
  67
  68     predictedCorrect
  69         .name(name() + ".predicted")
  70         .desc("Number of Branches Incorrectly Predicted");
  71
  72     mispredictPct
  73         .name(name() + ".mispredictPct")
  74         .desc("Percentage of Incorrect Branches Predicts")
  75         .precision(6);
  76     mispredictPct = (predictedIncorrect /
  77                      (predictedCorrect + predictedIncorrect)) * 100;
  78
  79     Resource::regStats();
  80 }
  81
  82 void
  83 ExecutionUnit::execute(int slot_num)
  84 {
  85     ResourceRequest* exec_req = reqs[slot_num];
  86     DynInstPtr inst = reqs[slot_num]->inst;
  87     Fault fault = NoFault;
  88     int seq_num = inst->seqNum;
  89
  90     DPRINTF(InOrderExecute, "[tid:%i] Executing [sn:%i] [PC:%s] %s.\n",
  91             inst->readTid(), seq_num, inst->pcState(), inst->instName());
  92
  93     switch (exec_req->cmd)
  94     {
  95       case ExecuteInst:
  96         {
  97             if (curTick() != lastExecuteTick) {
  98                 lastExecuteTick = curTick();
  99             }
 100
 101
 102             if (inst->isMemRef()) {
 103                 panic("%s not configured to handle memory ops.\n", resName);
 104             } else if (inst->isControl()) {
 105                 if (lastControlTick == curTick()) {
 106                     DPRINTF(InOrderExecute, "Can not Execute More than One Control "
 107                             "Inst Per Cycle. Blocking Request.\n");
 108                     exec_req->done(false);
 109                     return;
 110                 }
 111                 lastControlTick = curTick();
 112
 113                 // Evaluate Branch
 114                 fault = inst->execute();
 115                 executions++;
 116
 117                 inst->setExecuted();
 118
 119                 if (fault == NoFault) {
 120                     // If branch is mispredicted, then signal squash
 121                     // throughout all stages behind the pipeline stage
 122                     // that got squashed.
 123                     if (inst->mispredicted()) {
 124                         int stage_num = exec_req->getStageNum();
 125                         ThreadID tid = inst->readTid();
 126                         // If it's a branch ...
 127                         if (inst->isDirectCtrl()) {
 128                             assert(!inst->isIndirectCtrl());
 129
 130                             TheISA::PCState pc = inst->pcState();
 131                             TheISA::advancePC(pc, inst->staticInst);
 132                             inst->setPredTarg(pc);
 133
 134                             if (inst->predTaken() && inst->isCondDelaySlot()) {
 135                                 inst->bdelaySeqNum = seq_num;
 136
 137                                 DPRINTF(InOrderExecute, "[tid:%i]: Conditional"
 138                                         " branch inst [sn:%i] PC %s mis"
 139                                         "predicted as taken.\n", tid,
 140                                         seq_num, inst->pcState());
 141                             } else if (!inst->predTaken() &&
 142                                        inst->isCondDelaySlot()) {
 143                                 inst->bdelaySeqNum = seq_num;
 144                                 inst->procDelaySlotOnMispred = true;
 145
 146                                 DPRINTF(InOrderExecute, "[tid:%i]: Conditional"
 147                                         " branch inst [sn:%i] PC %s mis"
 148                                         "predicted as not taken.\n", tid,
 149                                         seq_num, inst->pcState());
 150                             } else {
 151 #if ISA_HAS_DELAY_SLOT
 152                                 inst->bdelaySeqNum = seq_num + 1;
 153 #else
 154                                 inst->bdelaySeqNum = seq_num;
 155 #endif
 156                                 DPRINTF(InOrderExecute, "[tid:%i]: "
 157                                         "Misprediction detected at "
 158                                         "[sn:%i] PC %s,\n\t squashing after "
 159                                         "delay slot instruction [sn:%i].\n",
 160                                         tid, seq_num, inst->pcState(),
 161                                         inst->bdelaySeqNum);
 162                                 DPRINTF(InOrderStall, "STALL: [tid:%i]: Branch"
 163                                         " misprediction at %s\n",
 164                                         tid, inst->pcState());
 165                             }
 166
 167                             DPRINTF(InOrderExecute, "[tid:%i] Redirecting "
 168                                     "fetch to %s.\n", tid,
 169                                     inst->readPredTarg());
 170
 171                         } else if (inst->isIndirectCtrl()){
 172                             TheISA::PCState pc = inst->pcState();
 173                             TheISA::advancePC(pc, inst->staticInst);
 174                             inst->seqNum = seq_num;
 175                             inst->setPredTarg(pc);
 176
 177 #if ISA_HAS_DELAY_SLOT
 178                             inst->bdelaySeqNum = seq_num + 1;
 179 #else
 180                             inst->bdelaySeqNum = seq_num;
 181 #endif
 182
 183                             DPRINTF(InOrderExecute, "[tid:%i] Redirecting"
 184                                     " fetch to %s.\n", tid,
 185                                     inst->readPredTarg());
 186                         } else {
 187                             panic("Non-control instruction (%s) mispredict"
 188                                   "ing?!!", inst->staticInst->getName());
 189                         }
 190
 191                         DPRINTF(InOrderExecute, "[tid:%i] Squashing will "
 192                                 "start from stage %i.\n", tid, stage_num);
 193
 194                         cpu->pipelineStage[stage_num]->squashDueToBranch(inst,
 195                                                                          tid);
 196
 197                         inst->squashingStage = stage_num;
 198
 199                         // Squash throughout other resources
 200                         cpu->resPool->scheduleEvent((InOrderCPU::CPUEventType)
 201                                                     ResourcePool::SquashAll,
 202                                                     inst, 0, 0, tid);
 203
 204                         if (inst->predTaken()) {
 205                             predictedTakenIncorrect++;
 206                             DPRINTF(InOrderExecute, "[tid:%i] [sn:%i] %s ..."
 207                                     "PC %s ... Mispredicts! (Taken)\n",
 208                                     tid, inst->seqNum,
 209                                     inst->staticInst->disassemble(
 210                                         inst->instAddr()),
 211                                     inst->pcState());
 212                         } else {
 213                             predictedNotTakenIncorrect++;
 214                             DPRINTF(InOrderExecute, "[tid:%i] [sn:%i] %s ..."
 215                                     "PC %s ... Mispredicts! (Not Taken)\n",
 216                                     tid, inst->seqNum,
 217                                     inst->staticInst->disassemble(
 218                                         inst->instAddr()),
 219                                     inst->pcState());
 220                         }
 221                         predictedIncorrect++;
 222                     } else {
 223                         DPRINTF(InOrderExecute, "[tid:%i]: [sn:%i]: Prediction"
 224                                 "Correct.\n", inst->readTid(), seq_num);
 225                         predictedCorrect++;
 226                     }
 227
 228                     exec_req->done();
 229                 } else {
 230                     warn("inst [sn:%i] had a %s fault",
 231                          seq_num, fault->name());
 232                 }
 233             } else {
 234                 // Regular ALU instruction
 235                 fault = inst->execute();
 236                 executions++;
 237
 238                 if (fault == NoFault) {
 239                     inst->setExecuted();
 240
 241                     DPRINTF(InOrderExecute, "[tid:%i]: [sn:%i]: The result "
 242                             "of execution is 0x%x.\n", inst->readTid(),
 243                             seq_num,
 244                             (inst->resultType(0) == InOrderDynInst::Float) ?
 245                             inst->readFloatResult(0) : inst->readIntResult(0));
 246                 } else {
 247                     DPRINTF(InOrderExecute, "[tid:%i]: [sn:%i]: had a %s "
 248                             "fault.\n", inst->readTid(), seq_num, fault->name());
 249                     inst->fault = fault;
 250                 }
 251
 252                 exec_req->done();
 253             }
 254         }
 255         break;
 256
 257       default:
 258         fatal("Unrecognized command to %s", resName);
 259     }
 260 }
 261
 262