src/cpu/inorder/resources/execution_unit.cc

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #include <vector>
  33 #include <list>
  34 #include "cpu/inorder/resources/execution_unit.hh"
  35 #include "cpu/inorder/resource_pool.hh"
  36 #include "cpu/inorder/cpu.hh"
  37
  38 using namespace std;
  39 using namespace ThePipeline;
  40
  41 ExecutionUnit::ExecutionUnit(string res_name, int res_id, int res_width,
  42                  int res_latency, InOrderCPU *_cpu, ThePipeline::Params *params)
  43     : Resource(res_name, res_id, res_width, res_latency, _cpu)
  44 { }
  45
  46 void
  47 ExecutionUnit::regStats()
  48 {
  49     predictedTakenIncorrect
  50         .name(name() + ".predictedTakenIncorrect")
  51         .desc("Number of Branches Incorrectly Predicted As Taken.");
  52
  53     predictedNotTakenIncorrect
  54         .name(name() + ".predictedNotTakenIncorrect")
  55         .desc("Number of Branches Incorrectly Predicted As Not Taken).");
  56
  57     lastExecuteCycle = curTick;
  58
  59     executions
  60         .name(name() + ".executions")
  61         .desc("Number of Instructions Executed.");
  62
  63     Resource::regStats();
  64 }
  65
  66 void
  67 ExecutionUnit::execute(int slot_num)
  68 {
  69     ResourceRequest* exec_req = reqMap[slot_num];
  70     DynInstPtr inst = reqMap[slot_num]->inst;
  71     Fault fault = reqMap[slot_num]->fault;
  72     ThreadID tid = inst->readTid();
  73     int seq_num = inst->seqNum;
  74
  75     exec_req->fault = NoFault;
  76
  77     DPRINTF(InOrderExecute, "[tid:%i] Executing [sn:%i] [PC:%#x] %s.\n",
  78             tid, seq_num, inst->readPC(), inst->instName());
  79
  80     switch (exec_req->cmd)
  81     {
  82       case ExecuteInst:
  83         {
  84             if (curTick != lastExecuteCycle) {
  85                 lastExecuteCycle = curTick;
  86             }
  87
  88
  89             if (inst->isMemRef()) {
  90                 panic("%s not configured to handle memory ops.\n", resName);
  91             } else if (inst->isControl()) {
  92                 // Evaluate Branch
  93                 fault = inst->execute();
  94                 executions++;
  95
  96                 inst->setExecuted();
  97
  98                 if (fault == NoFault) {
  99                     // If branch is mispredicted, then signal squash
 100                     // throughout all stages behind the pipeline stage
 101                     // that got squashed.
 102                     if (inst->mispredicted()) {
 103                         int stage_num = exec_req->getStageNum();
 104                         ThreadID tid = inst->readTid();
 105
 106                         // If it's a branch ...
 107                         if (inst->isDirectCtrl()) {
 108                             assert(!inst->isIndirectCtrl());
 109
 110                             if (inst->predTaken() && inst->isCondDelaySlot()) {
 111                                 inst->bdelaySeqNum = seq_num;
 112                                 inst->setPredTarg(inst->nextPC);
 113
 114                                 DPRINTF(InOrderExecute, "[tid:%i]: Conditional branch inst"
 115                                         "[sn:%i] PC %#x mispredicted as taken.\n", tid,
 116                                         seq_num, inst->PC);
 117                             } else if (!inst->predTaken() && inst->isCondDelaySlot()) {
 118                                 inst->bdelaySeqNum = seq_num;
 119                                 inst->setPredTarg(inst->nextPC);
 120                                 inst->procDelaySlotOnMispred = true;
 121
 122                                 DPRINTF(InOrderExecute, "[tid:%i]: Conditional branch inst."
 123                                         "[sn:%i] PC %#x mispredicted as not taken.\n", tid,
 124                                         seq_num, inst->PC);
 125                             } else {
 126 #if ISA_HAS_DELAY_SLOT
 127                                 inst->bdelaySeqNum = seq_num + 1;
 128                                 inst->setPredTarg(inst->nextNPC);
 129 #else
 130                                 inst->bdelaySeqNum = seq_num;
 131                                 inst->setPredTarg(inst->nextPC);
 132 #endif
 133                                 DPRINTF(InOrderExecute, "[tid:%i]: Misprediction detected at "
 134                                         "[sn:%i] PC %#x,\n\t squashing after delay slot "
 135                                         "instruction [sn:%i].\n",
 136                                         tid, seq_num, inst->PC, inst->bdelaySeqNum);
 137                                 DPRINTF(InOrderStall, "STALL: [tid:%i]: Branch "
 138                                         "misprediction at %#x\n", tid, inst->PC);
 139                             }
 140
 141                             DPRINTF(InOrderExecute, "[tid:%i] Redirecting fetch to %#x.\n", tid,
 142                                     inst->readPredTarg());
 143
 144                         } else if(inst->isIndirectCtrl()){
 145 #if ISA_HAS_DELAY_SLOT
 146                             inst->setPredTarg(inst->nextNPC);
 147                             inst->bdelaySeqNum = seq_num + 1;
 148 #else
 149                             inst->setPredTarg(inst->nextPC);
 150                             inst->bdelaySeqNum = seq_num;
 151 #endif
 152
 153                             DPRINTF(InOrderExecute, "[tid:%i] Redirecting fetch to %#x.\n", tid,
 154                                     inst->readPredTarg());
 155                         } else {
 156                             panic("Non-control instruction (%s) mispredicting?!!",
 157                                   inst->staticInst->getName());
 158                         }
 159
 160                         DPRINTF(InOrderExecute, "[tid:%i] Squashing will start from stage %i.\n",
 161                                 tid, stage_num);
 162
 163                         cpu->pipelineStage[stage_num]->squashDueToBranch(inst, tid);
 164
 165                         inst->squashingStage = stage_num;
 166
 167                         // Squash throughout other resources
 168                         cpu->resPool->scheduleEvent((InOrderCPU::CPUEventType)ResourcePool::SquashAll,
 169                                                     inst, 0, 0, tid);
 170
 171                         if (inst->predTaken()) {
 172                             predictedTakenIncorrect++;
 173                             DPRINTF(InOrderExecute, "[tid:%i] [sn:%i] %s ... PC%#x ... Mispredicts! (Taken)\n",
 174                                     tid, inst->seqNum, inst->staticInst->disassemble(inst->PC),
 175                                     inst->readPC());
 176                         } else {
 177                             predictedNotTakenIncorrect++;
 178                             DPRINTF(InOrderExecute, "[tid:%i] [sn:%i] %s ... PC%#x ... Mispredicts! (Not Taken)\n",
 179                                     tid, inst->seqNum, inst->staticInst->disassemble(inst->PC),
 180                                     inst->readPC());
 181                         }
 182                     } else {
 183                         DPRINTF(InOrderExecute, "[tid:%i]: [sn:%i]: Prediction Correct.\n",
 184                                 inst->readTid(), seq_num);
 185                     }
 186
 187                     exec_req->done();
 188                 } else {
 189                     warn("inst [sn:%i] had a %s fault", seq_num, fault->name());
 190                 }
 191             } else {
 192                 // Regular ALU instruction
 193                 fault = inst->execute();
 194                 executions++;
 195
 196                 if (fault == NoFault) {
 197                     inst->setExecuted();
 198
 199                     DPRINTF(InOrderExecute, "[tid:%i]: [sn:%i]: The result of execution is 0x%x.\n",
 200                             inst->readTid(), seq_num, (inst->resultType(0) == InOrderDynInst::Float) ?
 201                             inst->readFloatResult(0) : inst->readIntResult(0));
 202
 203                     exec_req->done();
 204                 } else {
 205                     warn("inst [sn:%i] had a %s fault", seq_num, fault->name());
 206                     cpu->trap(fault, tid);
 207                 }
 208             }
 209         }
 210         break;
 211
 212       default:
 213         fatal("Unrecognized command to %s", resName);
 214     }
 215 }
 216
 217