2 * Copyright (c) 2007 MIPS Technologies, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Korey Sewell
35 #include "cpu/inorder/resources/execution_unit.hh"
36 #include "cpu/inorder/cpu.hh"
37 #include "cpu/inorder/resource_pool.hh"
38 #include "debug/InOrderExecute.hh"
39 #include "debug/InOrderStall.hh"
42 using namespace ThePipeline
;
44 ExecutionUnit::ExecutionUnit(string res_name
, int res_id
, int res_width
,
45 int res_latency
, InOrderCPU
*_cpu
,
46 ThePipeline::Params
*params
)
47 : Resource(res_name
, res_id
, res_width
, res_latency
, _cpu
),
48 lastExecuteTick(0), lastControlTick(0), serializeTick(0)
52 ExecutionUnit::regStats()
54 predictedTakenIncorrect
55 .name(name() + ".predictedTakenIncorrect")
56 .desc("Number of Branches Incorrectly Predicted As Taken.");
58 predictedNotTakenIncorrect
59 .name(name() + ".predictedNotTakenIncorrect")
60 .desc("Number of Branches Incorrectly Predicted As Not Taken).");
63 .name(name() + ".executions")
64 .desc("Number of Instructions Executed.");
68 .name(name() + ".mispredicted")
69 .desc("Number of Branches Incorrectly Predicted");
72 .name(name() + ".predicted")
73 .desc("Number of Branches Incorrectly Predicted");
76 .name(name() + ".mispredictPct")
77 .desc("Percentage of Incorrect Branches Predicts")
79 mispredictPct
= (predictedIncorrect
/
80 (predictedCorrect
+ predictedIncorrect
)) * 100;
86 ExecutionUnit::execute(int slot_num
)
88 ResourceRequest
* exec_req
= reqs
[slot_num
];
89 DynInstPtr inst
= reqs
[slot_num
]->inst
;
90 Fault fault
= NoFault
;
91 InstSeqNum seq_num
= inst
->seqNum
;
92 Tick cur_tick
= curTick();
94 if (cur_tick
== serializeTick
) {
95 DPRINTF(InOrderExecute
, "Can not execute [tid:%i][sn:%i][PC:%s] %s. "
96 "All instructions are being serialized this cycle\n",
97 inst
->readTid(), seq_num
, inst
->pcState(), inst
->instName());
98 exec_req
->done(false);
103 switch (exec_req
->cmd
)
108 DPRINTF(InOrderExecute
, "[tid:%i] [sn:%i] [PC:%s] Ignoring execution"
109 "of %s.\n", inst
->readTid(), seq_num
, inst
->pcState(),
115 DPRINTF(InOrderExecute
, "[tid:%i] Executing [sn:%i] [PC:%s] %s.\n",
116 inst
->readTid(), seq_num
, inst
->pcState(), inst
->instName());
119 if (cur_tick
!= lastExecuteTick
) {
120 lastExecuteTick
= cur_tick
;
123 assert(!inst
->isMemRef());
125 if (inst
->isSerializeAfter()) {
126 serializeTick
= cur_tick
;
127 DPRINTF(InOrderExecute
, "Serializing execution after [tid:%i] "
128 "[sn:%i] [PC:%s] %s.\n", inst
->readTid(), seq_num
,
129 inst
->pcState(), inst
->instName());
132 if (inst
->isControl()) {
133 if (lastControlTick
== cur_tick
) {
134 DPRINTF(InOrderExecute
, "Can not Execute More than One Control "
135 "Inst Per Cycle. Blocking Request.\n");
136 exec_req
->done(false);
139 lastControlTick
= curTick();
142 DPRINTF(IEW
, "Pre-Execute %s PC:%s nextPC:%s predPC:%s\n", inst
->instName(), inst
->pcState(), inst
->readPredTarg());
143 fault
= inst
->execute();
146 DPRINTF(IEW
, "Post-Execute %s PC:%s nextPC:%s predPC:%s\n", inst
->instName(), inst
->pcState(), inst
->readPredTarg());
148 if (fault
== NoFault
) {
149 // If branch is mispredicted, then signal squash
150 // throughout all stages behind the pipeline stage
151 // that got squashed.
152 if (inst
->mispredicted()) {
153 int stage_num
= exec_req
->getStageNum();
154 ThreadID tid
= inst
->readTid();
155 // If it's a branch ...
156 if (inst
->isDirectCtrl()) {
157 assert(!inst
->isIndirectCtrl());
159 TheISA::PCState pc
= inst
->pcState();
160 TheISA::advancePC(pc
, inst
->staticInst
);
161 inst
->setPredTarg(pc
);
163 if (inst
->predTaken() && inst
->isCondDelaySlot()) {
164 assert(0 && "Not Handling Conditional Delay Slots (1)");
165 inst
->bdelaySeqNum
= seq_num
;
166 DPRINTF(InOrderExecute
, "[tid:%i]: Conditional"
167 " branch inst [sn:%i] PC %s mis"
168 "predicted as taken.\n", tid
,
169 seq_num
, inst
->pcState());
170 } else if (!inst
->predTaken() && inst
->isCondDelaySlot()) {
171 assert(0 && "Not Handling Conditional Delay Slots (2)");
172 inst
->bdelaySeqNum
= seq_num
;
173 inst
->procDelaySlotOnMispred
= true;
175 DPRINTF(InOrderExecute
, "[tid:%i]: Conditional"
176 " branch inst [sn:%i] PC %s mis"
177 "predicted as not taken.\n", tid
,
178 seq_num
, inst
->pcState());
180 #if ISA_HAS_DELAY_SLOT
181 inst
->bdelaySeqNum
= seq_num
+ 1;
183 inst
->bdelaySeqNum
= seq_num
;
185 DPRINTF(InOrderExecute
, "[tid:%i]: "
186 "Misprediction detected at "
187 "[sn:%i] PC %s,\n\t squashing after "
188 "delay slot instruction [sn:%i].\n",
189 tid
, seq_num
, inst
->pcState(),
191 DPRINTF(InOrderStall
, "STALL: [tid:%i]: Branch"
192 " misprediction at %s\n",
193 tid
, inst
->pcState());
196 DPRINTF(InOrderExecute
, "[tid:%i] Redirecting "
197 "fetch to %s.\n", tid
,
198 inst
->readPredTarg());
200 } else if (inst
->isIndirectCtrl()){
201 TheISA::PCState pc
= inst
->pcState();
202 TheISA::advancePC(pc
, inst
->staticInst
);
203 inst
->seqNum
= seq_num
;
204 inst
->setPredTarg(pc
);
206 #if ISA_HAS_DELAY_SLOT
207 inst
->bdelaySeqNum
= seq_num
+ 1;
209 inst
->bdelaySeqNum
= seq_num
;
212 DPRINTF(InOrderExecute
, "[tid:%i] Redirecting"
213 " fetch to %s.\n", tid
,
214 inst
->readPredTarg());
216 panic("Non-control instruction (%s) mispredict"
217 "ing?!!", inst
->staticInst
->getName());
220 DPRINTF(InOrderExecute
, "[tid:%i] Squashing will "
221 "start from stage %i.\n", tid
, stage_num
);
223 cpu
->pipelineStage
[stage_num
]->squashDueToBranch(inst
,
226 inst
->squashingStage
= stage_num
;
228 // Squash throughout other resources
229 cpu
->resPool
->scheduleEvent((InOrderCPU::CPUEventType
)
230 ResourcePool::SquashAll
,
233 if (inst
->predTaken()) {
234 predictedTakenIncorrect
++;
235 DPRINTF(InOrderExecute
, "[tid:%i] [sn:%i] %s ..."
236 "PC %s ... Mispredicts! (Taken)\n",
238 inst
->staticInst
->disassemble(
242 predictedNotTakenIncorrect
++;
243 DPRINTF(InOrderExecute
, "[tid:%i] [sn:%i] %s ..."
244 "PC %s ... Mispredicts! (Not Taken)\n",
246 inst
->staticInst
->disassemble(
250 predictedIncorrect
++;
252 DPRINTF(InOrderExecute
, "[tid:%i]: [sn:%i]: Prediction"
253 "Correct.\n", inst
->readTid(), seq_num
);
259 warn("inst [sn:%i] had a %s fault",
260 seq_num
, fault
->name());
263 // Regular ALU instruction
264 fault
= inst
->execute();
267 if (fault
== NoFault
) {
270 DPRINTF(InOrderExecute
, "[tid:%i]: [sn:%i]: The result "
271 "of execution is 0x%x.\n", inst
->readTid(),
273 (inst
->resultType(0) == InOrderDynInst::Float
) ?
274 inst
->readFloatResult(0) : inst
->readIntResult(0));
276 DPRINTF(InOrderExecute
, "[tid:%i]: [sn:%i]: had a %s "
277 "fault.\n", inst
->readTid(), seq_num
, fault
->name());
287 fatal("Unrecognized command to %s", resName
);