2 * Copyright (c) 2007 MIPS Technologies, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Korey Sewell
34 #include "cpu/inorder/resources/execution_unit.hh"
35 #include "cpu/inorder/resource_pool.hh"
36 #include "cpu/inorder/cpu.hh"
39 using namespace ThePipeline
;
41 ExecutionUnit::ExecutionUnit(string res_name
, int res_id
, int res_width
,
42 int res_latency
, InOrderCPU
*_cpu
,
43 ThePipeline::Params
*params
)
44 : Resource(res_name
, res_id
, res_width
, res_latency
, _cpu
),
45 lastExecuteTick(0), lastControlTick(0)
49 ExecutionUnit::regStats()
51 predictedTakenIncorrect
52 .name(name() + ".predictedTakenIncorrect")
53 .desc("Number of Branches Incorrectly Predicted As Taken.");
55 predictedNotTakenIncorrect
56 .name(name() + ".predictedNotTakenIncorrect")
57 .desc("Number of Branches Incorrectly Predicted As Not Taken).");
60 .name(name() + ".executions")
61 .desc("Number of Instructions Executed.");
65 .name(name() + ".mispredicted")
66 .desc("Number of Branches Incorrectly Predicted");
69 .name(name() + ".predicted")
70 .desc("Number of Branches Incorrectly Predicted");
73 .name(name() + ".mispredictPct")
74 .desc("Percentage of Incorrect Branches Predicts")
76 mispredictPct
= (predictedIncorrect
/
77 (predictedCorrect
+ predictedIncorrect
)) * 100;
83 ExecutionUnit::execute(int slot_num
)
85 ResourceRequest
* exec_req
= reqMap
[slot_num
];
86 DynInstPtr inst
= reqMap
[slot_num
]->inst
;
87 Fault fault
= NoFault
;
88 int seq_num
= inst
->seqNum
;
90 DPRINTF(InOrderExecute
, "[tid:%i] Executing [sn:%i] [PC:%s] %s.\n",
91 inst
->readTid(), seq_num
, inst
->pcState(), inst
->instName());
93 switch (exec_req
->cmd
)
97 if (curTick() != lastExecuteTick
) {
98 lastExecuteTick
= curTick();
102 if (inst
->isMemRef()) {
103 panic("%s not configured to handle memory ops.\n", resName
);
104 } else if (inst
->isControl()) {
105 if (lastControlTick
== curTick()) {
106 DPRINTF(InOrderExecute
, "Can not Execute More than One Control "
107 "Inst Per Cycle. Blocking Request.\n");
108 exec_req
->done(false);
111 lastControlTick
= curTick();
114 fault
= inst
->execute();
119 if (fault
== NoFault
) {
120 // If branch is mispredicted, then signal squash
121 // throughout all stages behind the pipeline stage
122 // that got squashed.
123 if (inst
->mispredicted()) {
124 int stage_num
= exec_req
->getStageNum();
125 ThreadID tid
= inst
->readTid();
126 // If it's a branch ...
127 if (inst
->isDirectCtrl()) {
128 assert(!inst
->isIndirectCtrl());
130 TheISA::PCState pc
= inst
->pcState();
131 TheISA::advancePC(pc
, inst
->staticInst
);
132 inst
->setPredTarg(pc
);
134 if (inst
->predTaken() && inst
->isCondDelaySlot()) {
135 inst
->bdelaySeqNum
= seq_num
;
137 DPRINTF(InOrderExecute
, "[tid:%i]: Conditional"
138 " branch inst [sn:%i] PC %s mis"
139 "predicted as taken.\n", tid
,
140 seq_num
, inst
->pcState());
141 } else if (!inst
->predTaken() &&
142 inst
->isCondDelaySlot()) {
143 inst
->bdelaySeqNum
= seq_num
;
144 inst
->procDelaySlotOnMispred
= true;
146 DPRINTF(InOrderExecute
, "[tid:%i]: Conditional"
147 " branch inst [sn:%i] PC %s mis"
148 "predicted as not taken.\n", tid
,
149 seq_num
, inst
->pcState());
151 #if ISA_HAS_DELAY_SLOT
152 inst
->bdelaySeqNum
= seq_num
+ 1;
154 inst
->bdelaySeqNum
= seq_num
;
156 DPRINTF(InOrderExecute
, "[tid:%i]: "
157 "Misprediction detected at "
158 "[sn:%i] PC %s,\n\t squashing after "
159 "delay slot instruction [sn:%i].\n",
160 tid
, seq_num
, inst
->pcState(),
162 DPRINTF(InOrderStall
, "STALL: [tid:%i]: Branch"
163 " misprediction at %s\n",
164 tid
, inst
->pcState());
167 DPRINTF(InOrderExecute
, "[tid:%i] Redirecting "
168 "fetch to %s.\n", tid
,
169 inst
->readPredTarg());
171 } else if (inst
->isIndirectCtrl()){
172 TheISA::PCState pc
= inst
->pcState();
173 TheISA::advancePC(pc
, inst
->staticInst
);
174 inst
->seqNum
= seq_num
;
175 inst
->setPredTarg(pc
);
177 #if ISA_HAS_DELAY_SLOT
178 inst
->bdelaySeqNum
= seq_num
+ 1;
180 inst
->bdelaySeqNum
= seq_num
;
183 DPRINTF(InOrderExecute
, "[tid:%i] Redirecting"
184 " fetch to %s.\n", tid
,
185 inst
->readPredTarg());
187 panic("Non-control instruction (%s) mispredict"
188 "ing?!!", inst
->staticInst
->getName());
191 DPRINTF(InOrderExecute
, "[tid:%i] Squashing will "
192 "start from stage %i.\n", tid
, stage_num
);
194 cpu
->pipelineStage
[stage_num
]->squashDueToBranch(inst
,
197 inst
->squashingStage
= stage_num
;
199 // Squash throughout other resources
200 cpu
->resPool
->scheduleEvent((InOrderCPU::CPUEventType
)
201 ResourcePool::SquashAll
,
204 if (inst
->predTaken()) {
205 predictedTakenIncorrect
++;
206 DPRINTF(InOrderExecute
, "[tid:%i] [sn:%i] %s ..."
207 "PC %s ... Mispredicts! (Taken)\n",
209 inst
->staticInst
->disassemble(
213 predictedNotTakenIncorrect
++;
214 DPRINTF(InOrderExecute
, "[tid:%i] [sn:%i] %s ..."
215 "PC %s ... Mispredicts! (Not Taken)\n",
217 inst
->staticInst
->disassemble(
221 predictedIncorrect
++;
223 DPRINTF(InOrderExecute
, "[tid:%i]: [sn:%i]: Prediction"
224 "Correct.\n", inst
->readTid(), seq_num
);
230 warn("inst [sn:%i] had a %s fault",
231 seq_num
, fault
->name());
234 // Regular ALU instruction
235 fault
= inst
->execute();
238 if (fault
== NoFault
) {
241 DPRINTF(InOrderExecute
, "[tid:%i]: [sn:%i]: The result "
242 "of execution is 0x%x.\n", inst
->readTid(),
244 (inst
->resultType(0) == InOrderDynInst::Float
) ?
245 inst
->readFloatResult(0) : inst
->readIntResult(0));
247 DPRINTF(InOrderExecute
, "[tid:%i]: [sn:%i]: had a %s "
248 "fault.\n", inst
->readTid(), seq_num
, fault
->name());
258 fatal("Unrecognized command to %s", resName
);