src/cpu/inorder/resources/execution_unit.cc

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #include <list>
  33 #include <vector>
  34
  35 #include "cpu/inorder/resources/execution_unit.hh"
  36 #include "cpu/inorder/cpu.hh"
  37 #include "cpu/inorder/resource_pool.hh"
  38 #include "debug/Fault.hh"
  39 #include "debug/InOrderExecute.hh"
  40 #include "debug/InOrderStall.hh"
  41
  42 using namespace std;
  43 using namespace ThePipeline;
  44
  45 ExecutionUnit::ExecutionUnit(string res_name, int res_id, int res_width,
  46                              int res_latency, InOrderCPU *_cpu,
  47                              ThePipeline::Params *params)
  48     : Resource(res_name, res_id, res_width, res_latency, _cpu),
  49       lastExecuteTick(0), lastControlTick(0)
  50 { }
  51
  52 void
  53 ExecutionUnit::regStats()
  54 {
  55     predictedTakenIncorrect
  56         .name(name() + ".predictedTakenIncorrect")
  57         .desc("Number of Branches Incorrectly Predicted As Taken.");
  58
  59     predictedNotTakenIncorrect
  60         .name(name() + ".predictedNotTakenIncorrect")
  61         .desc("Number of Branches Incorrectly Predicted As Not Taken).");
  62
  63     executions
  64         .name(name() + ".executions")
  65         .desc("Number of Instructions Executed.");
  66
  67
  68     predictedIncorrect
  69         .name(name() + ".mispredicted")
  70         .desc("Number of Branches Incorrectly Predicted");
  71
  72     predictedCorrect
  73         .name(name() + ".predicted")
  74         .desc("Number of Branches Incorrectly Predicted");
  75
  76     mispredictPct
  77         .name(name() + ".mispredictPct")
  78         .desc("Percentage of Incorrect Branches Predicts")
  79         .precision(6);
  80     mispredictPct = (predictedIncorrect /
  81                      (predictedCorrect + predictedIncorrect)) * 100;
  82
  83     Resource::regStats();
  84 }
  85
  86 void
  87 ExecutionUnit::execute(int slot_num)
  88 {
  89     ResourceRequest* exec_req = reqs[slot_num];
  90     DynInstPtr inst = reqs[slot_num]->inst;
  91     if (inst->fault != NoFault) {
  92         DPRINTF(InOrderExecute,
  93                 "[tid:%i]: [sn:%i]: Detected %s fault @ %x. Forwarding to "
  94                 "next stage.\n", inst->readTid(), inst->seqNum, inst->fault->name(),
  95                 inst->pcState());
  96         exec_req->done();
  97         return;
  98     }
  99
 100     Fault fault = NoFault;
 101     Tick cur_tick = curTick();
 102     unsigned stage_num = exec_req->getStageNum();
 103     ThreadID tid = inst->readTid();
 104 #if TRACING_ON
 105     InstSeqNum seq_num = inst->seqNum;
 106 #endif
 107
 108     switch (exec_req->cmd)
 109     {
 110       case ExecuteInst:
 111         {
 112             if (inst->isNop()) {
 113                 DPRINTF(InOrderExecute, "[tid:%i] [sn:%i] [PC:%s] Ignoring execution"
 114                         "of %s.\n", inst->readTid(), seq_num, inst->pcState(),
 115                         inst->instName());
 116                 inst->setExecuted();
 117                 exec_req->done();
 118                 return;
 119             } else {
 120                 DPRINTF(InOrderExecute, "[tid:%i] Executing [sn:%i] [PC:%s] %s.\n",
 121                         inst->readTid(), seq_num, inst->pcState(), inst->instName());
 122             }
 123
 124             if (cur_tick != lastExecuteTick) {
 125                 lastExecuteTick = cur_tick;
 126             }
 127
 128             //@todo: handle address generation here
 129             assert(!inst->isMemRef());
 130
 131             if (inst->isControl()) {
 132                 if (lastControlTick == cur_tick) {
 133                     DPRINTF(InOrderExecute, "Can not Execute More than One Control "
 134                             "Inst Per Cycle. Blocking Request.\n");
 135                     exec_req->done(false);
 136                     return;
 137                 }
 138                 lastControlTick = curTick();
 139
 140                 // Evaluate Branch
 141                 fault = inst->execute();
 142
 143                 // Should unconditional control , pc relative count as an
 144                 // execution??? Probably not.
 145                 executions++;
 146
 147                 if (fault == NoFault) {
 148                     inst->setExecuted();
 149
 150                     if (inst->mispredicted()) {
 151                         assert(inst->isControl());
 152
 153                         // Set up Squash Generated By this Misprediction
 154                         TheISA::PCState pc = inst->pcState();
 155                         TheISA::advancePC(pc, inst->staticInst);
 156                         inst->setPredTarg(pc);
 157                         inst->setSquashInfo(stage_num);
 158                         setupSquash(inst, stage_num, tid);
 159
 160                         DPRINTF(InOrderExecute, "[tid:%i]: [sn:%i] Squashing from "
 161                                 "stage %i. Redirecting  fetch to %s.\n", tid,
 162                                 inst->seqNum, stage_num, pc);
 163                         DPRINTF(InOrderStall, "STALL: [tid:%i]: Branch"
 164                                 " misprediction at %s\n", tid, inst->pcState());
 165
 166                         if (inst->predTaken()) {
 167                             predictedTakenIncorrect++;
 168                             DPRINTF(InOrderExecute, "[tid:%i] [sn:%i] %s ..."
 169                                     "PC %s ... Mispredicts! "
 170                                     "(Prediction: Taken)\n",
 171                                     tid, inst->seqNum,
 172                                     inst->staticInst->disassemble(
 173                                         inst->instAddr()),
 174                                     inst->pcState());
 175                         } else {
 176                             predictedNotTakenIncorrect++;
 177                             DPRINTF(InOrderExecute, "[tid:%i] [sn:%i] %s ..."
 178                                     "PC %s ... Mispredicts! "
 179                                     "(Prediction: Not Taken)\n",
 180                                     tid, inst->seqNum,
 181                                     inst->staticInst->disassemble(
 182                                         inst->instAddr()),
 183                                     inst->pcState());
 184                         }
 185                         predictedIncorrect++;
 186                     } else {
 187                         DPRINTF(InOrderExecute, "[tid:%i]: [sn:%i]: Prediction"
 188                                 "Correct.\n", inst->readTid(), seq_num);
 189                         predictedCorrect++;
 190                     }
 191
 192                     exec_req->done();
 193                 } else {
 194                     DPRINTF(Fault, "[tid:%i]:[sn:%i]: Fault %s found\n",
 195                             inst->readTid(), inst->seqNum, fault->name());
 196                     inst->fault = fault;
 197                     exec_req->done();
 198                 }
 199             } else {
 200                 // Regular ALU instruction
 201                 fault = inst->execute();
 202                 executions++;
 203
 204                 if (fault == NoFault) {
 205                     inst->setExecuted();
 206
 207 #if TRACING_ON
 208                     for (int didx = 0; didx < inst->numDestRegs(); didx++)
 209                         if (inst->resultType(didx) == InOrderDynInst::Float ||
 210                             inst->resultType(didx) == InOrderDynInst::FloatBits ||
 211                             inst->resultType(didx) == InOrderDynInst::Double)
 212                             DPRINTF(InOrderExecute, "[tid:%i]: [sn:%i]: Dest result %i "
 213                                     "of FP execution is %08f (%x).\n", inst->readTid(),
 214                                     seq_num, didx, inst->readFloatResult(didx),
 215                                     inst->readFloatBitsResult(didx));
 216                         else
 217                             DPRINTF(InOrderExecute, "[tid:%i]: [sn:%i]: Dest result %i "
 218                                     "of Int execution is 0x%x.\n", inst->readTid(),
 219                                     seq_num, didx, inst->readIntResult(didx));
 220 #endif
 221
 222 #if !FULL_SYSTEM
 223                     // The Syscall might change the PC, so conservatively
 224                     // squash everything behing it
 225                     if (inst->isSyscall()) {
 226                         inst->setSquashInfo(stage_num);
 227                         setupSquash(inst, stage_num, tid);
 228                     }
 229 #endif
 230                 } else {
 231                     DPRINTF(InOrderExecute, "[tid:%i]: [sn:%i]: had a %s "
 232                             "fault.\n", inst->readTid(), seq_num, fault->name());
 233                     DPRINTF(Fault, "[tid:%i]:[sn:%i]: Fault %s found\n",
 234                             inst->readTid(), inst->seqNum, fault->name());
 235                     inst->fault = fault;
 236                 }
 237
 238                 exec_req->done();
 239             }
 240         }
 241         break;
 242
 243       default:
 244         fatal("Unrecognized command to %s", resName);
 245     }
 246 }
 247
 248