2 * Copyright (c) 2007 MIPS Technologies, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Korey Sewell
32 #include "config/the_isa.hh"
33 #include "cpu/inorder/resources/fetch_seq_unit.hh"
34 #include "cpu/inorder/resource_pool.hh"
37 using namespace TheISA
;
38 using namespace ThePipeline
;
40 FetchSeqUnit::FetchSeqUnit(std::string res_name
, int res_id
, int res_width
,
41 int res_latency
, InOrderCPU
*_cpu
,
42 ThePipeline::Params
*params
)
43 : Resource(res_name
, res_id
, res_width
, res_latency
, _cpu
),
44 instSize(sizeof(MachInst
))
46 for (ThreadID tid
= 0; tid
< ThePipeline::MaxThreads
; tid
++) {
48 pcBlockStage
[tid
] = 0;
50 squashSeqNum
[tid
] = (InstSeqNum
)-1;
51 lastSquashCycle
[tid
] = 0;
55 FetchSeqUnit::~FetchSeqUnit()
57 delete [] resourceEvent
;
63 resourceEvent
= new FetchSeqEvent
[width
];
69 FetchSeqUnit::execute(int slot_num
)
71 // After this is working, change this to a reinterpret cast
72 // for performance considerations
73 ResourceRequest
* fs_req
= reqMap
[slot_num
];
74 DynInstPtr inst
= fs_req
->inst
;
75 ThreadID tid
= inst
->readTid();
76 int stage_num
= fs_req
->getStageNum();
77 int seq_num
= inst
->seqNum
;
79 fs_req
->fault
= NoFault
;
86 inst
->pcState(pc
[tid
]);
87 inst
->setMemAddr(pc
[tid
].instAddr());
89 pc
[tid
].advance(); //XXX HACK!
90 inst
->setPredTarg(pc
[tid
]);
92 inst
->setSeqNum(cpu
->getAndIncrementInstSeq(tid
));
94 DPRINTF(InOrderFetchSeq
, "[tid:%i]: Assigning [sn:%i] to "
95 "PC %s\n", tid
, inst
->seqNum
,
100 DPRINTF(InOrderStall
, "STALL: [tid:%i]: NPC not valid\n", tid
);
101 fs_req
->setCompleted(false);
108 if (inst
->isControl()) {
109 // If it's a return, then we must wait for resolved address.
110 if (inst
->isReturn() && !inst
->predTaken()) {
111 cpu
->pipelineStage
[stage_num
]->
112 toPrevStages
->stageBlock
[stage_num
][tid
] = true;
113 pcValid
[tid
] = false;
114 pcBlockStage
[tid
] = stage_num
;
115 } else if (inst
->isCondDelaySlot() && !inst
->predTaken()) {
116 // Not-Taken AND Conditional Control
117 DPRINTF(InOrderFetchSeq
, "[tid:%i]: [sn:%i]: [PC:%s] "
118 "Predicted Not-Taken Cond. Delay inst. Skipping "
119 "delay slot and Updating PC to %s\n",
120 tid
, inst
->seqNum
, inst
->pcState(),
121 inst
->readPredTarg());
123 DPRINTF(InOrderFetchSeq
, "[tid:%i] Setting up squash to "
124 "start from stage %i, after [sn:%i].\n", tid
,
127 inst
->bdelaySeqNum
= seq_num
;
128 inst
->squashingStage
= stage_num
;
130 squashAfterInst(inst
, stage_num
, tid
);
131 } else if (!inst
->isCondDelaySlot() && !inst
->predTaken()) {
133 DPRINTF(InOrderFetchSeq
, "[tid:%i]: [sn:%i]: Predicted "
135 "inst. updating PC to %s\n", tid
, inst
->seqNum
,
136 inst
->readPredTarg());
137 #if ISA_HAS_DELAY_SLOT
138 pc
[tid
] = inst
->pcState();
139 advancePC(pc
[tid
], inst
->staticInst
);
141 } else if (inst
->predTaken()) {
143 #if ISA_HAS_DELAY_SLOT
144 pc
[tid
] = inst
->readPredTarg();
146 DPRINTF(InOrderFetchSeq
, "[tid:%i]: [sn:%i] Updating delay"
147 " slot target to PC %s\n", tid
, inst
->seqNum
,
148 inst
->readPredTarg());
149 inst
->bdelaySeqNum
= seq_num
+ 1;
151 inst
->bdelaySeqNum
= seq_num
;
154 inst
->squashingStage
= stage_num
;
155 DPRINTF(InOrderFetchSeq
, "[tid:%i] Setting up squash to "
156 "start from stage %i, after [sn:%i].\n",
157 tid
, stage_num
, inst
->bdelaySeqNum
);
160 squashAfterInst(inst
, stage_num
, tid
);
163 DPRINTF(InOrderFetchSeq
, "[tid:%i]: [sn:%i]: Ignoring branch "
164 "target update since then is not a control "
165 "instruction.\n", tid
, inst
->seqNum
);
173 fatal("Unrecognized command to %s", resName
);
178 FetchSeqUnit::squashAfterInst(DynInstPtr inst
, int stage_num
, ThreadID tid
)
180 // Squash In Pipeline Stage
181 cpu
->pipelineStage
[stage_num
]->squashDueToBranch(inst
, tid
);
183 // Squash inside current resource, so if there needs to be fetching on
184 // same cycle the fetch information will be correct.
186 // Schedule Squash Through-out Resource Pool
187 cpu
->resPool
->scheduleEvent(
188 (InOrderCPU::CPUEventType
)ResourcePool::SquashAll
, inst
, 0);
192 FetchSeqUnit::squash(DynInstPtr inst
, int squash_stage
,
193 InstSeqNum squash_seq_num
, ThreadID tid
)
195 DPRINTF(InOrderFetchSeq
, "[tid:%i]: Updating due to squash from stage %i."
196 "\n", tid
, squash_stage
);
198 InstSeqNum done_seq_num
= inst
->bdelaySeqNum
;
200 // Handles the case where we are squashing because of something that is
201 // not a branch...like a memory stall
202 TheISA::PCState newPC
;
203 if (inst
->isControl()) {
204 newPC
= inst
->readPredTarg();
206 TheISA::PCState thisPC
= inst
->pcState();
207 assert(inst
->staticInst
);
208 advancePC(thisPC
, inst
->staticInst
);
212 if (squashSeqNum
[tid
] <= done_seq_num
&&
213 lastSquashCycle
[tid
] == curTick()) {
214 DPRINTF(InOrderFetchSeq
, "[tid:%i]: Ignoring squash from stage %i, "
215 "since there is an outstanding squash that is older.\n",
218 squashSeqNum
[tid
] = done_seq_num
;
219 lastSquashCycle
[tid
] = curTick();
221 // If The very next instruction number is the done seq. num,
222 // then we haven't seen the delay slot yet ... if it isn't
223 // the last done_seq_num then this is the delay slot inst.
224 if (cpu
->nextInstSeqNum(tid
) != done_seq_num
&&
225 !inst
->procDelaySlotOnMispred
) {
229 #if ISA_HAS_DELAY_SLOT
230 TheISA::advancePC(pc
[tid
], inst
->staticInst
);
233 DPRINTF(InOrderFetchSeq
, "[tid:%i]: Setting PC to %s.\n",
236 assert(ISA_HAS_DELAY_SLOT
);
238 pc
[tid
] = (inst
->procDelaySlotOnMispred
) ?
239 inst
->branchTarget() : newPC
;
241 // Reset PC to Delay Slot Instruction
242 if (inst
->procDelaySlotOnMispred
) {
249 // Unblock Any Stages Waiting for this information to be updated ...
251 cpu
->pipelineStage
[pcBlockStage
[tid
]]->
252 toPrevStages
->stageUnblock
[pcBlockStage
[tid
]][tid
] = true;
258 Resource::squash(inst
, squash_stage
, squash_seq_num
, tid
);
261 FetchSeqUnit::FetchSeqEvent::FetchSeqEvent()
266 FetchSeqUnit::FetchSeqEvent::process()
268 FetchSeqUnit
* fs_res
= dynamic_cast<FetchSeqUnit
*>(resource
);
271 for (int i
= 0; i
< MaxThreads
; i
++) {
272 fs_res
->pc
[i
] = fs_res
->cpu
->pcState(i
);
273 DPRINTF(InOrderFetchSeq
, "[tid:%i]: Setting PC: %s.\n",
276 fs_res
->pcValid
[i
] = true;
282 FetchSeqUnit::activateThread(ThreadID tid
)
286 pc
[tid
] = cpu
->pcState(tid
);
288 cpu
->fetchPriorityList
.push_back(tid
);
290 DPRINTF(InOrderFetchSeq
, "[tid:%i]: Reading PC: %s.\n",
295 FetchSeqUnit::deactivateThread(ThreadID tid
)
297 pcValid
[tid
] = false;
298 pcBlockStage
[tid
] = 0;
300 squashSeqNum
[tid
] = (InstSeqNum
)-1;
301 lastSquashCycle
[tid
] = 0;
303 list
<ThreadID
>::iterator thread_it
= find(cpu
->fetchPriorityList
.begin(),
304 cpu
->fetchPriorityList
.end(),
307 if (thread_it
!= cpu
->fetchPriorityList
.end())
308 cpu
->fetchPriorityList
.erase(thread_it
);
312 FetchSeqUnit::suspendThread(ThreadID tid
)
314 deactivateThread(tid
);
318 FetchSeqUnit::updateAfterContextSwitch(DynInstPtr inst
, ThreadID tid
)
322 if (cpu
->thread
[tid
]->lastGradIsBranch
) {
323 /** This function assumes that the instruction causing the context
324 * switch was right after the branch. Thus, if it's not, then
325 * we are updating incorrectly here
327 assert(cpu
->nextInstAddr(tid
) == inst
->instAddr());
328 pc
[tid
] = cpu
->thread
[tid
]->lastBranchPC
;
330 pc
[tid
] = inst
->pcState();
332 assert(inst
->staticInst
);
333 advancePC(pc
[tid
], inst
->staticInst
);
335 DPRINTF(InOrderFetchSeq
, "[tid:%i]: Updating PCs due to Context Switch."
336 "Assigning PC: %s.\n", tid
, pc
[tid
]);