src/cpu/inorder/resources/fetch_seq_unit.cc

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #include "config/the_isa.hh"
  33 #include "cpu/inorder/resources/fetch_seq_unit.hh"
  34 #include "cpu/inorder/resource_pool.hh"
  35
  36 using namespace std;
  37 using namespace TheISA;
  38 using namespace ThePipeline;
  39
  40 FetchSeqUnit::FetchSeqUnit(std::string res_name, int res_id, int res_width,
  41                            int res_latency, InOrderCPU *_cpu,
  42                            ThePipeline::Params *params)
  43     : Resource(res_name, res_id, res_width, res_latency, _cpu),
  44       instSize(sizeof(MachInst))
  45 {
  46     for (ThreadID tid = 0; tid < ThePipeline::MaxThreads; tid++) {
  47         pcValid[tid] = false;
  48         pcBlockStage[tid] = 0;
  49
  50         squashSeqNum[tid] = (InstSeqNum)-1;
  51         lastSquashCycle[tid] = 0;
  52     }
  53 }
  54
  55 FetchSeqUnit::~FetchSeqUnit()
  56 {
  57     delete [] resourceEvent;
  58 }
  59
  60 void
  61 FetchSeqUnit::init()
  62 {
  63     resourceEvent = new FetchSeqEvent[width];
  64
  65     initSlots();
  66 }
  67
  68 void
  69 FetchSeqUnit::execute(int slot_num)
  70 {
  71     // After this is working, change this to a reinterpret cast
  72     // for performance considerations
  73     ResourceRequest* fs_req = reqMap[slot_num];
  74     DynInstPtr inst = fs_req->inst;
  75     ThreadID tid = inst->readTid();
  76     int stage_num = fs_req->getStageNum();
  77     int seq_num = inst->seqNum;
  78
  79     fs_req->fault = NoFault;
  80
  81     switch (fs_req->cmd)
  82     {
  83       case AssignNextPC:
  84         {
  85             if (pcValid[tid]) {
  86                 inst->pcState(pc[tid]);
  87                 inst->setMemAddr(pc[tid].instAddr());
  88
  89                 pc[tid].advance(); //XXX HACK!
  90                 inst->setPredTarg(pc[tid]);
  91
  92                 inst->setSeqNum(cpu->getAndIncrementInstSeq(tid));
  93
  94                 DPRINTF(InOrderFetchSeq, "[tid:%i]: Assigning [sn:%i] to "
  95                         "PC %s\n", tid, inst->seqNum,
  96                         inst->pcState());
  97
  98                 fs_req->done();
  99             } else {
 100                 DPRINTF(InOrderStall, "STALL: [tid:%i]: NPC not valid\n", tid);
 101                 fs_req->setCompleted(false);
 102             }
 103         }
 104         break;
 105
 106       case UpdateTargetPC:
 107         {
 108             if (inst->isControl()) {
 109                 // If it's a return, then we must wait for resolved address.
 110                 if (inst->isReturn() && !inst->predTaken()) {
 111                     cpu->pipelineStage[stage_num]->
 112                         toPrevStages->stageBlock[stage_num][tid] = true;
 113                     pcValid[tid] = false;
 114                     pcBlockStage[tid] = stage_num;
 115                 } else if (inst->isCondDelaySlot() && !inst->predTaken()) {
 116                 // Not-Taken AND Conditional Control
 117                     DPRINTF(InOrderFetchSeq, "[tid:%i]: [sn:%i]: [PC:%s] "
 118                             "Predicted Not-Taken Cond. Delay inst. Skipping "
 119                             "delay slot and  Updating PC to %s\n",
 120                             tid, inst->seqNum, inst->pcState(),
 121                             inst->readPredTarg());
 122
 123                     DPRINTF(InOrderFetchSeq, "[tid:%i] Setting up squash to "
 124                             "start from stage %i, after [sn:%i].\n", tid,
 125                             stage_num, seq_num);
 126
 127                     inst->bdelaySeqNum = seq_num;
 128                     inst->squashingStage = stage_num;
 129
 130                     squashAfterInst(inst, stage_num, tid);
 131                 } else if (!inst->isCondDelaySlot() && !inst->predTaken()) {
 132                     // Not-Taken Control
 133                     DPRINTF(InOrderFetchSeq, "[tid:%i]: [sn:%i]: Predicted "
 134                             "Not-Taken Control "
 135                             "inst. updating PC to %s\n", tid, inst->seqNum,
 136                             inst->readPredTarg());
 137 #if ISA_HAS_DELAY_SLOT
 138                     pc[tid] = inst->pcState();
 139                     advancePC(pc[tid], inst->staticInst);
 140 #endif
 141                 } else if (inst->predTaken()) {
 142                     // Taken Control
 143 #if ISA_HAS_DELAY_SLOT
 144                     pc[tid] = inst->readPredTarg();
 145
 146                     DPRINTF(InOrderFetchSeq, "[tid:%i]: [sn:%i] Updating delay"
 147                             " slot target to PC %s\n", tid, inst->seqNum,
 148                             inst->readPredTarg());
 149                     inst->bdelaySeqNum = seq_num + 1;
 150 #else
 151                     inst->bdelaySeqNum = seq_num;
 152 #endif
 153
 154                     inst->squashingStage = stage_num;
 155                     DPRINTF(InOrderFetchSeq, "[tid:%i] Setting up squash to "
 156                             "start from stage %i, after [sn:%i].\n",
 157                             tid, stage_num, inst->bdelaySeqNum);
 158
 159                     // Do Squashing
 160                     squashAfterInst(inst, stage_num, tid);
 161                 }
 162             } else {
 163                 DPRINTF(InOrderFetchSeq, "[tid:%i]: [sn:%i]: Ignoring branch "
 164                         "target update since then is not a control "
 165                         "instruction.\n", tid, inst->seqNum);
 166             }
 167
 168             fs_req->done();
 169         }
 170         break;
 171
 172       default:
 173         fatal("Unrecognized command to %s", resName);
 174     }
 175 }
 176
 177 inline void
 178 FetchSeqUnit::squashAfterInst(DynInstPtr inst, int stage_num, ThreadID tid)
 179 {
 180     // Squash In Pipeline Stage
 181     cpu->pipelineStage[stage_num]->squashDueToBranch(inst, tid);
 182
 183     // Squash inside current resource, so if there needs to be fetching on
 184     // same cycle the fetch information will be correct.
 185
 186     // Schedule Squash Through-out Resource Pool
 187     cpu->resPool->scheduleEvent(
 188             (InOrderCPU::CPUEventType)ResourcePool::SquashAll, inst, 0);
 189 }
 190
 191 void
 192 FetchSeqUnit::squash(DynInstPtr inst, int squash_stage,
 193                      InstSeqNum squash_seq_num, ThreadID tid)
 194 {
 195     DPRINTF(InOrderFetchSeq, "[tid:%i]: Updating due to squash from stage %i."
 196             "\n", tid, squash_stage);
 197
 198     InstSeqNum done_seq_num = inst->bdelaySeqNum;
 199
 200     // Handles the case where we are squashing because of something that is
 201     // not a branch...like a memory stall
 202     TheISA::PCState newPC;
 203     if (inst->isControl()) {
 204         newPC = inst->readPredTarg();
 205     } else {
 206         TheISA::PCState thisPC = inst->pcState();
 207         assert(inst->staticInst);
 208         advancePC(thisPC, inst->staticInst);
 209         newPC = thisPC;
 210     }
 211
 212     if (squashSeqNum[tid] <= done_seq_num &&
 213         lastSquashCycle[tid] == curTick) {
 214         DPRINTF(InOrderFetchSeq, "[tid:%i]: Ignoring squash from stage %i, "
 215                 "since there is an outstanding squash that is older.\n",
 216                 tid, squash_stage);
 217     } else {
 218         squashSeqNum[tid] = done_seq_num;
 219         lastSquashCycle[tid] = curTick;
 220
 221         // If The very next instruction number is the done seq. num,
 222         // then we haven't seen the delay slot yet ... if it isn't
 223         // the last done_seq_num then this is the delay slot inst.
 224         if (cpu->nextInstSeqNum(tid) != done_seq_num &&
 225             !inst->procDelaySlotOnMispred) {
 226
 227             // Reset PC
 228             pc[tid] = newPC;
 229 #if ISA_HAS_DELAY_SLOT
 230             TheISA::advancePC(pc[tid], inst->staticInst);
 231 #endif
 232
 233             DPRINTF(InOrderFetchSeq, "[tid:%i]: Setting PC to %s.\n",
 234                     tid, newPC);
 235         } else {
 236             assert(ISA_HAS_DELAY_SLOT);
 237
 238             pc[tid] = (inst->procDelaySlotOnMispred) ?
 239                 inst->branchTarget() : newPC;
 240
 241             // Reset PC to Delay Slot Instruction
 242             if (inst->procDelaySlotOnMispred) {
 243                 // Reset PC
 244                 pc[tid] = newPC;
 245             }
 246
 247         }
 248
 249         // Unblock Any Stages Waiting for this information to be updated ...
 250         if (!pcValid[tid]) {
 251             cpu->pipelineStage[pcBlockStage[tid]]->
 252                 toPrevStages->stageUnblock[pcBlockStage[tid]][tid] = true;
 253         }
 254
 255         pcValid[tid] = true;
 256     }
 257
 258     Resource::squash(inst, squash_stage, squash_seq_num, tid);
 259 }
 260
 261 FetchSeqUnit::FetchSeqEvent::FetchSeqEvent()
 262     : ResourceEvent()
 263 { }
 264
 265 void
 266 FetchSeqUnit::FetchSeqEvent::process()
 267 {
 268     FetchSeqUnit* fs_res = dynamic_cast<FetchSeqUnit*>(resource);
 269     assert(fs_res);
 270
 271     for (int i = 0; i < MaxThreads; i++) {
 272         fs_res->pc[i] = fs_res->cpu->pcState(i);
 273         DPRINTF(InOrderFetchSeq, "[tid:%i]: Setting PC: %s.\n",
 274                 fs_res->pc[i]);
 275
 276         fs_res->pcValid[i] = true;
 277     }
 278 }
 279
 280
 281 void
 282 FetchSeqUnit::activateThread(ThreadID tid)
 283 {
 284     pcValid[tid] = true;
 285
 286     pc[tid] = cpu->pcState(tid);
 287
 288     cpu->fetchPriorityList.push_back(tid);
 289
 290     DPRINTF(InOrderFetchSeq, "[tid:%i]: Reading PC: %s.\n",
 291             tid, pc[tid]);
 292 }
 293
 294 void
 295 FetchSeqUnit::deactivateThread(ThreadID tid)
 296 {
 297     pcValid[tid] = false;
 298     pcBlockStage[tid] = 0;
 299
 300     squashSeqNum[tid] = (InstSeqNum)-1;
 301     lastSquashCycle[tid] = 0;
 302
 303     list<ThreadID>::iterator thread_it = find(cpu->fetchPriorityList.begin(),
 304                                               cpu->fetchPriorityList.end(),
 305                                               tid);
 306
 307     if (thread_it != cpu->fetchPriorityList.end())
 308         cpu->fetchPriorityList.erase(thread_it);
 309 }
 310
 311 void
 312 FetchSeqUnit::suspendThread(ThreadID tid)
 313 {
 314     deactivateThread(tid);
 315 }
 316
 317 void
 318 FetchSeqUnit::updateAfterContextSwitch(DynInstPtr inst, ThreadID tid)
 319 {
 320     pcValid[tid] = true;
 321
 322     if (cpu->thread[tid]->lastGradIsBranch) {
 323         /** This function assumes that the instruction causing the context
 324          *  switch was right after the branch. Thus, if it's not, then
 325          *  we are updating incorrectly here
 326          */
 327         assert(cpu->nextInstAddr(tid) == inst->instAddr());
 328         pc[tid] = cpu->thread[tid]->lastBranchPC;
 329     } else {
 330         pc[tid] = inst->pcState();
 331     }
 332     assert(inst->staticInst);
 333     advancePC(pc[tid], inst->staticInst);
 334
 335     DPRINTF(InOrderFetchSeq, "[tid:%i]: Updating PCs due to Context Switch."
 336             "Assigning  PC: %s.\n", tid, pc[tid]);
 337 }