src/cpu/inorder/resources/fetch_seq_unit.cc

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #include "cpu/inorder/resources/fetch_seq_unit.hh"
  33 #include "cpu/inorder/resource_pool.hh"
  34
  35 using namespace std;
  36 using namespace TheISA;
  37 using namespace ThePipeline;
  38
  39 FetchSeqUnit::FetchSeqUnit(std::string res_name, int res_id, int res_width,
  40                        int res_latency, InOrderCPU *_cpu, ThePipeline::Params *params)
  41     : Resource(res_name, res_id, res_width, res_latency, _cpu)
  42 {
  43     instSize = sizeof(MachInst);
  44
  45     for (int tid = 0; tid < ThePipeline::MaxThreads; tid++) {
  46         delaySlotInfo[tid].numInsts = 0;
  47         delaySlotInfo[tid].targetReady = false;
  48
  49         pcValid[tid] = false;
  50         pcBlockStage[tid] = 0;
  51
  52         squashSeqNum[tid] = (InstSeqNum)-1;
  53         lastSquashCycle[tid] = 0;
  54     }
  55 }
  56
  57 void
  58 FetchSeqUnit::init()
  59 {
  60     resourceEvent = new FetchSeqEvent[width];
  61
  62     initSlots();
  63 }
  64
  65 void
  66 FetchSeqUnit::execute(int slot_num)
  67 {
  68     // After this is working, change this to a reinterpret cast
  69     // for performance considerations
  70     ResourceRequest* fs_req = reqMap[slot_num];
  71     DynInstPtr inst = fs_req->inst;
  72     int tid = inst->readTid();
  73     int stage_num = fs_req->getStageNum();
  74     int seq_num = inst->seqNum;
  75
  76     fs_req->fault = NoFault;
  77
  78     switch (fs_req->cmd)
  79     {
  80       case AssignNextPC:
  81         {
  82             if (pcValid[tid]) {
  83
  84                 if (delaySlotInfo[tid].targetReady &&
  85                     delaySlotInfo[tid].numInsts == 0) {
  86                     // Set PC to target
  87                     PC[tid] = delaySlotInfo[tid].targetAddr; //next_PC
  88                     nextPC[tid] = PC[tid] + instSize;        //next_NPC
  89                     nextNPC[tid] = PC[tid] + (2 * instSize);
  90
  91                     delaySlotInfo[tid].targetReady = false;
  92
  93                     DPRINTF(InOrderFetchSeq, "[tid:%i]: Setting PC to delay slot target\n",tid);
  94                 }
  95
  96                 inst->setPC(PC[tid]);
  97                 inst->setNextPC(PC[tid] + instSize);
  98                 inst->setNextNPC(PC[tid] + (instSize * 2));
  99
 100                 inst->setPredTarg(inst->readNextNPC());
 101
 102                 inst->setMemAddr(PC[tid]);
 103                 inst->setSeqNum(cpu->getAndIncrementInstSeq(tid));
 104
 105                 DPRINTF(InOrderFetchSeq, "[tid:%i]: Assigning [sn:%i] to PC %08p\n", tid,
 106                         inst->seqNum, inst->readPC());
 107
 108                 if (delaySlotInfo[tid].numInsts > 0) {
 109                     --delaySlotInfo[tid].numInsts;
 110
 111                     // It's OK to set PC to target of branch
 112                     if (delaySlotInfo[tid].numInsts == 0) {
 113                         delaySlotInfo[tid].targetReady = true;
 114                     }
 115
 116                     DPRINTF(InOrderFetchSeq, "[tid:%i]: %i delay slot inst(s) left to"
 117                             " process.\n", tid, delaySlotInfo[tid].numInsts);
 118                 }
 119
 120                 PC[tid] = nextPC[tid];
 121                 nextPC[tid] = nextNPC[tid];
 122                 nextNPC[tid] += instSize;
 123
 124                 fs_req->done();
 125             } else {
 126                 DPRINTF(InOrderStall, "STALL: [tid:%i]: NPC not valid\n", tid);
 127                 fs_req->setCompleted(false);
 128             }
 129         }
 130         break;
 131
 132       case UpdateTargetPC:
 133         {
 134             if (inst->isControl()) {
 135                 // If it's a return, then we must wait for resolved address.
 136                 if (inst->isReturn() && !inst->predTaken()) {
 137                     cpu->pipelineStage[stage_num]->toPrevStages->stageBlock[stage_num][tid] = true;
 138                     pcValid[tid] = false;
 139                     pcBlockStage[tid] = stage_num;
 140                 } else if (inst->isCondDelaySlot() && !inst->predTaken()) {
 141                 // Not-Taken AND Conditional Control
 142                     DPRINTF(InOrderFetchSeq, "[tid:%i]: [sn:%i]: [PC:%08p] Predicted Not-Taken Cond. "
 143                             "Delay inst. Skipping delay slot and  Updating PC to %08p\n",
 144                             tid, inst->seqNum, inst->readPC(), inst->readPredTarg());
 145
 146                     DPRINTF(InOrderFetchSeq, "[tid:%i] Setting up squash to start from stage %i, after [sn:%i].\n",
 147                             tid, stage_num, seq_num);
 148
 149                     inst->bdelaySeqNum = seq_num;
 150                     inst->squashingStage = stage_num;
 151
 152                     squashAfterInst(inst, stage_num, tid);
 153                 } else if (!inst->isCondDelaySlot() && !inst->predTaken()) {
 154                 // Not-Taken Control
 155                     DPRINTF(InOrderFetchSeq, "[tid:%i]: [sn:%i]: Predicted Not-Taken Control "
 156                             "inst. updating PC to %08p\n", tid, inst->seqNum,
 157                             inst->readNextPC());
 158
 159                     ++delaySlotInfo[tid].numInsts;
 160                     delaySlotInfo[tid].targetReady = false;
 161                     delaySlotInfo[tid].targetAddr = inst->readNextNPC();
 162
 163                 } else if (inst->predTaken()) {
 164                 // Taken Control
 165                     ++delaySlotInfo[tid].numInsts;
 166                     delaySlotInfo[tid].targetReady = false;
 167                     delaySlotInfo[tid].targetAddr = inst->readPredTarg();
 168
 169                     DPRINTF(InOrderFetchSeq, "[tid:%i]: [sn:%i] Updating delay slot target "
 170                             "to PC %08p\n", tid, inst->seqNum, inst->readPredTarg());
 171
 172                     // Set-Up Squash Through-Out Pipeline
 173                     DPRINTF(InOrderFetchSeq, "[tid:%i] Setting up squash to start from stage %i, after [sn:%i].\n",
 174                             tid, stage_num, seq_num + 1);
 175                     inst->bdelaySeqNum = seq_num + 1;
 176                     inst->squashingStage = stage_num;
 177
 178                     // Do Squashing
 179                     squashAfterInst(inst, stage_num, tid);
 180                 }
 181             } else {
 182                 DPRINTF(InOrderFetchSeq, "[tid:%i]: [sn:%i]: Ignoring branch target update "
 183                         "since then is not a control instruction.\n", tid, inst->seqNum);
 184             }
 185
 186             fs_req->done();
 187         }
 188         break;
 189
 190       default:
 191         fatal("Unrecognized command to %s", resName);
 192     }
 193 }
 194
 195 inline void
 196 FetchSeqUnit::squashAfterInst(DynInstPtr inst, int stage_num, unsigned tid)
 197 {
 198     // Squash In Pipeline Stage
 199     cpu->pipelineStage[stage_num]->squashDueToBranch(inst, tid);
 200
 201     // Squash inside current resource, so if there needs to be fetching on same cycle
 202     // the fetch information will be correct.
 203     // squash(inst, stage_num, inst->bdelaySeqNum, tid);
 204
 205     // Schedule Squash Through-out Resource Pool
 206     cpu->resPool->scheduleEvent((InOrderCPU::CPUEventType)ResourcePool::SquashAll, inst, 0);
 207 }
 208 void
 209 FetchSeqUnit::squash(DynInstPtr inst, int squash_stage,
 210                      InstSeqNum squash_seq_num, unsigned tid)
 211 {
 212     DPRINTF(InOrderFetchSeq, "[tid:%i]: Updating due to squash from stage %i.\n",
 213             tid, squash_stage);
 214
 215     InstSeqNum done_seq_num = inst->bdelaySeqNum;
 216     Addr new_PC = inst->readPredTarg();
 217
 218     if (squashSeqNum[tid] <= done_seq_num &&
 219         lastSquashCycle[tid] == curTick) {
 220         DPRINTF(InOrderFetchSeq, "[tid:%i]: Ignoring squash from stage %i, since"
 221                 "there is an outstanding squash that is older.\n",
 222                 tid, squash_stage);
 223     } else {
 224         squashSeqNum[tid] = done_seq_num;
 225         lastSquashCycle[tid] = curTick;
 226
 227         // If The very next instruction number is the done seq. num,
 228         // then we haven't seen the delay slot yet ... if it isn't
 229         // the last done_seq_num then this is the delay slot inst.
 230         if (cpu->nextInstSeqNum(tid) != done_seq_num &&
 231             !inst->procDelaySlotOnMispred) {
 232             delaySlotInfo[tid].numInsts = 0;
 233             delaySlotInfo[tid].targetReady = false;
 234
 235             // Reset PC
 236             PC[tid] = new_PC;
 237             nextPC[tid] = new_PC + instSize;
 238             nextNPC[tid] = new_PC + (2 * instSize);
 239
 240             DPRINTF(InOrderFetchSeq, "[tid:%i]: Setting PC to %08p.\n",
 241                     tid, PC[tid]);
 242         } else {
 243             delaySlotInfo[tid].numInsts = 1;
 244             delaySlotInfo[tid].targetReady = false;
 245             delaySlotInfo[tid].targetAddr = (inst->procDelaySlotOnMispred) ? inst->branchTarget() : new_PC;
 246
 247             // Reset PC to Delay Slot Instruction
 248             if (inst->procDelaySlotOnMispred) {
 249                 PC[tid] = new_PC;
 250                 nextPC[tid] = new_PC + instSize;
 251                 nextNPC[tid] = new_PC + (2 * instSize);
 252             }
 253
 254         }
 255
 256         // Unblock Any Stages Waiting for this information to be updated ...
 257         if (!pcValid[tid]) {
 258             cpu->pipelineStage[pcBlockStage[tid]]->toPrevStages->stageUnblock[pcBlockStage[tid]][tid] = true;
 259         }
 260
 261         pcValid[tid] = true;
 262     }
 263
 264     Resource::squash(inst, squash_stage, squash_seq_num, tid);
 265 }
 266
 267 FetchSeqUnit::FetchSeqEvent::FetchSeqEvent()
 268     : ResourceEvent()
 269 { }
 270
 271 void
 272 FetchSeqUnit::FetchSeqEvent::process()
 273 {
 274     FetchSeqUnit* fs_res = dynamic_cast<FetchSeqUnit*>(resource);
 275     assert(fs_res);
 276
 277     for (int i=0; i < MaxThreads; i++) {
 278         fs_res->PC[i] = fs_res->cpu->readPC(i);
 279         fs_res->nextPC[i] = fs_res->cpu->readNextPC(i);
 280         fs_res->nextNPC[i] = fs_res->cpu->readNextNPC(i);
 281         DPRINTF(InOrderFetchSeq, "[tid:%i]: Setting PC:%08p NPC:%08p NNPC:%08p.\n",
 282                 fs_res->PC[i], fs_res->nextPC[i], fs_res->nextNPC[i]);
 283
 284         fs_res->pcValid[i] = true;
 285     }
 286
 287     //cpu->fetchPriorityList.push_back(tid);
 288 }
 289
 290
 291 void
 292 FetchSeqUnit::activateThread(unsigned tid)
 293 {
 294     pcValid[tid] = true;
 295
 296     PC[tid] = cpu->readPC(tid);
 297     nextPC[tid] = cpu->readNextPC(tid);
 298     nextNPC[tid] = cpu->readNextNPC(tid);
 299
 300     cpu->fetchPriorityList.push_back(tid);
 301
 302     DPRINTF(InOrderFetchSeq, "[tid:%i]: Reading PC:%08p NPC:%08p NNPC:%08p.\n",
 303             tid, PC[tid], nextPC[tid], nextNPC[tid]);
 304 }
 305
 306 void
 307 FetchSeqUnit::deactivateThread(unsigned tid)
 308 {
 309     delaySlotInfo[tid].numInsts = 0;
 310     delaySlotInfo[tid].targetReady = false;
 311
 312     pcValid[tid] = false;
 313     pcBlockStage[tid] = 0;
 314
 315     squashSeqNum[tid] = (InstSeqNum)-1;
 316     lastSquashCycle[tid] = 0;
 317
 318     std::list<unsigned>::iterator thread_it = find(cpu->fetchPriorityList.begin(),
 319                                               cpu->fetchPriorityList.end(),
 320                                               tid);
 321
 322     if (thread_it != cpu->fetchPriorityList.end())
 323         cpu->fetchPriorityList.erase(thread_it);
 324 }