src/cpu/inorder/resources/fetch_seq_unit.cc

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #include "config/the_isa.hh"
  33 #include "cpu/inorder/resources/fetch_seq_unit.hh"
  34 #include "cpu/inorder/resource_pool.hh"
  35 #include "debug/InOrderFetchSeq.hh"
  36 #include "debug/InOrderStall.hh"
  37
  38 using namespace std;
  39 using namespace TheISA;
  40 using namespace ThePipeline;
  41
  42 FetchSeqUnit::FetchSeqUnit(std::string res_name, int res_id, int res_width,
  43                            int res_latency, InOrderCPU *_cpu,
  44                            ThePipeline::Params *params)
  45     : Resource(res_name, res_id, res_width, res_latency, _cpu),
  46       instSize(sizeof(MachInst))
  47 {
  48     for (ThreadID tid = 0; tid < ThePipeline::MaxThreads; tid++) {
  49         pcValid[tid] = false;
  50         pcBlockStage[tid] = 0;
  51
  52         squashSeqNum[tid] = (InstSeqNum)-1;
  53         lastSquashCycle[tid] = 0;
  54     }
  55 }
  56
  57 FetchSeqUnit::~FetchSeqUnit()
  58 {
  59     delete [] resourceEvent;
  60 }
  61
  62 void
  63 FetchSeqUnit::init()
  64 {
  65     resourceEvent = new FetchSeqEvent[width];
  66
  67     for (int i = 0; i < width; i++) {
  68         reqs[i] = new ResourceRequest(this);
  69     }
  70
  71     initSlots();
  72 }
  73
  74 void
  75 FetchSeqUnit::execute(int slot_num)
  76 {
  77     ResourceRequest* fs_req = reqs[slot_num];
  78     DynInstPtr inst = fs_req->inst;
  79     ThreadID tid = inst->readTid();
  80     int stage_num = fs_req->getStageNum();
  81
  82     DPRINTF(InOrderFetchSeq, "[tid:%i]: Current PC is %s\n", tid,
  83             pc[tid]);
  84
  85     switch (fs_req->cmd)
  86     {
  87       case AssignNextPC:
  88         {
  89             if (pcValid[tid]) {
  90                 inst->pcState(pc[tid]);
  91                 inst->setMemAddr(pc[tid].instAddr());
  92
  93                 // Advance to next PC (typically PC + 4)
  94                 pc[tid].advance();
  95
  96                 inst->setSeqNum(cpu->getAndIncrementInstSeq(tid));
  97
  98                 DPRINTF(InOrderFetchSeq, "[tid:%i]: Assigning [sn:%i] to "
  99                         "PC %s\n", tid, inst->seqNum, inst->pcState());
 100
 101                 fs_req->done();
 102             } else {
 103                 DPRINTF(InOrderStall, "STALL: [tid:%i]: NPC not valid\n", tid);
 104                 fs_req->done(false);
 105             }
 106         }
 107         break;
 108
 109       case UpdateTargetPC:
 110         {
 111             assert(!inst->isCondDelaySlot()  &&
 112                    "Not Handling Conditional Delay Slot");
 113
 114             if (inst->isControl()) {
 115                 if (inst->isReturn() && !inst->predTaken()) {
 116                     // If it's a return, then we must wait for resolved address.
 117                     // The Predictor will mark a return a false as "not taken"
 118                     // if there is no RAS entry
 119                     cpu->pipelineStage[stage_num]->
 120                         toPrevStages->stageBlock[stage_num][tid] = true;
 121                     pcValid[tid] = false;
 122                     pcBlockStage[tid] = stage_num;
 123                 } else if (inst->predTaken()) {
 124                     // Taken Control
 125                     inst->setSquashInfo(stage_num);
 126                     setupSquash(inst, stage_num, tid);
 127
 128                     DPRINTF(InOrderFetchSeq, "[tid:%i] Setting up squash to "
 129                             "start from stage %i, after [sn:%i].\n",
 130                             tid, stage_num, inst->squashSeqNum);
 131                 }
 132             } else {
 133                 DPRINTF(InOrderFetchSeq, "[tid:%i]: [sn:%i]: Ignoring branch "
 134                         "target update since then is not a control "
 135                         "instruction.\n", tid, inst->seqNum);
 136             }
 137
 138             fs_req->done();
 139         }
 140         break;
 141
 142       default:
 143         fatal("Unrecognized command to %s", resName);
 144     }
 145 }
 146
 147 void
 148 FetchSeqUnit::squash(DynInstPtr inst, int squash_stage,
 149                      InstSeqNum squash_seq_num, ThreadID tid)
 150 {
 151     DPRINTF(InOrderFetchSeq, "[tid:%i]: Updating due to squash from %s (%s) "
 152             "stage %i.\n", tid, inst->instName(), inst->pcState(),
 153             squash_stage);
 154
 155     if (lastSquashCycle[tid] == curTick() &&
 156         squashSeqNum[tid] <= squash_seq_num) {
 157         DPRINTF(InOrderFetchSeq, "[tid:%i]: Ignoring squash from stage %i, "
 158                 "since there is an outstanding squash that is older.\n",
 159                 tid, squash_stage);
 160     } else {
 161         squashSeqNum[tid] = squash_seq_num;
 162         lastSquashCycle[tid] = curTick();
 163
 164         if (inst->fault != NoFault) {
 165             // A Trap Caused This Fault and will update the pc state
 166             // when done trapping
 167             DPRINTF(InOrderFetchSeq, "[tid:%i] Blocking due to fault @ "
 168                     "[sn:%i].\n", inst->seqNum);
 169             pcValid[tid] = false;
 170         } else {
 171             TheISA::PCState nextPC;
 172             assert(inst->staticInst);
 173             if (inst->isControl()) {
 174                 nextPC = inst->readPredTarg();
 175
 176                 // If we are already fetching this PC then advance to next PC
 177                 // =======
 178                 // This should handle ISAs w/delay slots and annulled delay
 179                 // slots to figure out which is the next PC to fetch after
 180                 // a mispredict
 181                 DynInstPtr bdelay_inst = NULL;
 182                 ListIt bdelay_it;
 183                 if (inst->onInstList) {
 184                     bdelay_it = inst->getInstListIt();
 185                     bdelay_it++;
 186                 } else {
 187                     InstSeqNum branch_delay_num = inst->seqNum + 1;
 188                     bdelay_it = cpu->findInst(branch_delay_num, tid);
 189                 }
 190
 191                 if (bdelay_it != cpu->instList[tid].end()) {
 192                     bdelay_inst = (*bdelay_it);
 193                 }
 194
 195                 if (bdelay_inst) {
 196                     DPRINTF(Resource, "Evaluating %s v. %s\n",
 197                             bdelay_inst->pc, nextPC);
 198
 199                     if (bdelay_inst->pc.instAddr() == nextPC.instAddr()) {
 200                         advancePC(nextPC, inst->staticInst);
 201                         DPRINTF(Resource, "Advanced PC to %s\n", nextPC);
 202                     }
 203                 }
 204              } else {
 205                 nextPC = inst->pcState();
 206                 advancePC(nextPC, inst->staticInst);
 207             }
 208
 209
 210             DPRINTF(InOrderFetchSeq, "[tid:%i]: Setting PC to %s.\n",
 211                     tid, nextPC);
 212             pc[tid] = nextPC;
 213
 214             // Unblock Any Stages Waiting for this information to be updated ...
 215             if (!pcValid[tid]) {
 216                 cpu->pipelineStage[pcBlockStage[tid]]->
 217                     toPrevStages->stageUnblock[pcBlockStage[tid]][tid] = true;
 218             }
 219
 220             pcValid[tid] = true;
 221         }
 222      }
 223
 224     Resource::squash(inst, squash_stage, squash_seq_num, tid);
 225 }
 226
 227 FetchSeqUnit::FetchSeqEvent::FetchSeqEvent()
 228     : ResourceEvent()
 229 { }
 230
 231 void
 232 FetchSeqUnit::FetchSeqEvent::process()
 233 {
 234     FetchSeqUnit* fs_res = dynamic_cast<FetchSeqUnit*>(resource);
 235     assert(fs_res);
 236
 237     for (int i = 0; i < MaxThreads; i++) {
 238         fs_res->pc[i] = fs_res->cpu->pcState(i);
 239         DPRINTF(InOrderFetchSeq, "[tid:%i]: Setting PC: %s.\n",
 240                 fs_res->pc[i]);
 241
 242         fs_res->pcValid[i] = true;
 243     }
 244 }
 245
 246
 247 void
 248 FetchSeqUnit::activateThread(ThreadID tid)
 249 {
 250     pcValid[tid] = true;
 251
 252     pc[tid] = cpu->pcState(tid);
 253
 254     cpu->fetchPriorityList.push_back(tid);
 255
 256     DPRINTF(InOrderFetchSeq, "[tid:%i]: Reading PC: %s.\n",
 257             tid, pc[tid]);
 258 }
 259
 260 void
 261 FetchSeqUnit::deactivateThread(ThreadID tid)
 262 {
 263     pcValid[tid] = false;
 264     pcBlockStage[tid] = 0;
 265
 266     squashSeqNum[tid] = (InstSeqNum)-1;
 267     lastSquashCycle[tid] = 0;
 268
 269     list<ThreadID>::iterator thread_it = find(cpu->fetchPriorityList.begin(),
 270                                               cpu->fetchPriorityList.end(),
 271                                               tid);
 272
 273     if (thread_it != cpu->fetchPriorityList.end())
 274         cpu->fetchPriorityList.erase(thread_it);
 275 }
 276
 277 void
 278 FetchSeqUnit::suspendThread(ThreadID tid)
 279 {
 280     deactivateThread(tid);
 281 }
 282
 283 void
 284 FetchSeqUnit::trap(Fault fault, ThreadID tid, DynInstPtr inst)
 285 {
 286     pcValid[tid] = true;
 287     pc[tid] = cpu->pcState(tid);
 288     DPRINTF(Fault, "[tid:%i]: Trap updating to PC: "
 289             "%s.\n", tid, pc[tid]);
 290     DPRINTF(InOrderFetchSeq, "[tid:%i]: Trap updating to PC: "
 291             "%s.\n", tid, pc[tid]);
 292 }
 293
 294 void
 295 FetchSeqUnit::updateAfterContextSwitch(DynInstPtr inst, ThreadID tid)
 296 {
 297     pcValid[tid] = true;
 298
 299     if (cpu->thread[tid]->lastGradIsBranch) {
 300         /** This function assumes that the instruction causing the context
 301          *  switch was right after the branch. Thus, if it's not, then
 302          *  we are updating incorrectly here
 303          */
 304         assert(cpu->nextInstAddr(tid) == inst->instAddr());
 305         pc[tid] = cpu->thread[tid]->lastBranchPC;
 306     } else {
 307         pc[tid] = inst->pcState();
 308     }
 309     assert(inst->staticInst);
 310     advancePC(pc[tid], inst->staticInst);
 311
 312     DPRINTF(InOrderFetchSeq, "[tid:%i]: Updating PCs due to Context Switch."
 313             "Assigning  PC: %s.\n", tid, pc[tid]);
 314 }