src/cpu/inorder/resources/fetch_seq_unit.cc

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #include "cpu/inorder/resources/fetch_seq_unit.hh"
  33 #include "cpu/inorder/resource_pool.hh"
  34
  35 using namespace std;
  36 using namespace TheISA;
  37 using namespace ThePipeline;
  38
  39 FetchSeqUnit::FetchSeqUnit(std::string res_name, int res_id, int res_width,
  40                        int res_latency, InOrderCPU *_cpu, ThePipeline::Params *params)
  41     : Resource(res_name, res_id, res_width, res_latency, _cpu),
  42       instSize(sizeof(MachInst))
  43 {
  44     for (int tid = 0; tid < ThePipeline::MaxThreads; tid++) {
  45         delaySlotInfo[tid].numInsts = 0;
  46         delaySlotInfo[tid].targetReady = false;
  47
  48         pcValid[tid] = false;
  49         pcBlockStage[tid] = 0;
  50
  51         squashSeqNum[tid] = (InstSeqNum)-1;
  52         lastSquashCycle[tid] = 0;
  53     }
  54 }
  55
  56 void
  57 FetchSeqUnit::init()
  58 {
  59     resourceEvent = new FetchSeqEvent[width];
  60
  61     initSlots();
  62 }
  63
  64 void
  65 FetchSeqUnit::execute(int slot_num)
  66 {
  67     // After this is working, change this to a reinterpret cast
  68     // for performance considerations
  69     ResourceRequest* fs_req = reqMap[slot_num];
  70     DynInstPtr inst = fs_req->inst;
  71     int tid = inst->readTid();
  72     int stage_num = fs_req->getStageNum();
  73     int seq_num = inst->seqNum;
  74
  75     fs_req->fault = NoFault;
  76
  77     switch (fs_req->cmd)
  78     {
  79       case AssignNextPC:
  80         {
  81             if (pcValid[tid]) {
  82
  83                 if (delaySlotInfo[tid].targetReady &&
  84                     delaySlotInfo[tid].numInsts == 0) {
  85                     // Set PC to target
  86                     PC[tid] = delaySlotInfo[tid].targetAddr; //next_PC
  87                     nextPC[tid] = PC[tid] + instSize;        //next_NPC
  88                     nextNPC[tid] = PC[tid] + (2 * instSize);
  89
  90                     delaySlotInfo[tid].targetReady = false;
  91
  92                     DPRINTF(InOrderFetchSeq, "[tid:%i]: Setting PC to delay slot target\n",tid);
  93                 }
  94
  95                 inst->setPC(PC[tid]);
  96                 inst->setNextPC(PC[tid] + instSize);
  97                 inst->setNextNPC(PC[tid] + (instSize * 2));
  98
  99                 inst->setPredTarg(inst->readNextNPC());
 100
 101                 inst->setMemAddr(PC[tid]);
 102                 inst->setSeqNum(cpu->getAndIncrementInstSeq(tid));
 103
 104                 DPRINTF(InOrderFetchSeq, "[tid:%i]: Assigning [sn:%i] to PC %08p\n", tid,
 105                         inst->seqNum, inst->readPC());
 106
 107                 if (delaySlotInfo[tid].numInsts > 0) {
 108                     --delaySlotInfo[tid].numInsts;
 109
 110                     // It's OK to set PC to target of branch
 111                     if (delaySlotInfo[tid].numInsts == 0) {
 112                         delaySlotInfo[tid].targetReady = true;
 113                     }
 114
 115                     DPRINTF(InOrderFetchSeq, "[tid:%i]: %i delay slot inst(s) left to"
 116                             " process.\n", tid, delaySlotInfo[tid].numInsts);
 117                 }
 118
 119                 PC[tid] = nextPC[tid];
 120                 nextPC[tid] = nextNPC[tid];
 121                 nextNPC[tid] += instSize;
 122
 123                 fs_req->done();
 124             } else {
 125                 DPRINTF(InOrderStall, "STALL: [tid:%i]: NPC not valid\n", tid);
 126                 fs_req->setCompleted(false);
 127             }
 128         }
 129         break;
 130
 131       case UpdateTargetPC:
 132         {
 133             if (inst->isControl()) {
 134                 // If it's a return, then we must wait for resolved address.
 135                 if (inst->isReturn() && !inst->predTaken()) {
 136                     cpu->pipelineStage[stage_num]->toPrevStages->stageBlock[stage_num][tid] = true;
 137                     pcValid[tid] = false;
 138                     pcBlockStage[tid] = stage_num;
 139                 } else if (inst->isCondDelaySlot() && !inst->predTaken()) {
 140                 // Not-Taken AND Conditional Control
 141                     DPRINTF(InOrderFetchSeq, "[tid:%i]: [sn:%i]: [PC:%08p] Predicted Not-Taken Cond. "
 142                             "Delay inst. Skipping delay slot and  Updating PC to %08p\n",
 143                             tid, inst->seqNum, inst->readPC(), inst->readPredTarg());
 144
 145                     DPRINTF(InOrderFetchSeq, "[tid:%i] Setting up squash to start from stage %i, after [sn:%i].\n",
 146                             tid, stage_num, seq_num);
 147
 148                     inst->bdelaySeqNum = seq_num;
 149                     inst->squashingStage = stage_num;
 150
 151                     squashAfterInst(inst, stage_num, tid);
 152                 } else if (!inst->isCondDelaySlot() && !inst->predTaken()) {
 153                 // Not-Taken Control
 154                     DPRINTF(InOrderFetchSeq, "[tid:%i]: [sn:%i]: Predicted Not-Taken Control "
 155                             "inst. updating PC to %08p\n", tid, inst->seqNum,
 156                             inst->readNextPC());
 157
 158                     ++delaySlotInfo[tid].numInsts;
 159                     delaySlotInfo[tid].targetReady = false;
 160                     delaySlotInfo[tid].targetAddr = inst->readNextNPC();
 161
 162                 } else if (inst->predTaken()) {
 163                 // Taken Control
 164                     ++delaySlotInfo[tid].numInsts;
 165                     delaySlotInfo[tid].targetReady = false;
 166                     delaySlotInfo[tid].targetAddr = inst->readPredTarg();
 167
 168                     DPRINTF(InOrderFetchSeq, "[tid:%i]: [sn:%i] Updating delay slot target "
 169                             "to PC %08p\n", tid, inst->seqNum, inst->readPredTarg());
 170
 171                     // Set-Up Squash Through-Out Pipeline
 172                     DPRINTF(InOrderFetchSeq, "[tid:%i] Setting up squash to start from stage %i, after [sn:%i].\n",
 173                             tid, stage_num, seq_num + 1);
 174                     inst->bdelaySeqNum = seq_num + 1;
 175                     inst->squashingStage = stage_num;
 176
 177                     // Do Squashing
 178                     squashAfterInst(inst, stage_num, tid);
 179                 }
 180             } else {
 181                 DPRINTF(InOrderFetchSeq, "[tid:%i]: [sn:%i]: Ignoring branch target update "
 182                         "since then is not a control instruction.\n", tid, inst->seqNum);
 183             }
 184
 185             fs_req->done();
 186         }
 187         break;
 188
 189       default:
 190         fatal("Unrecognized command to %s", resName);
 191     }
 192 }
 193
 194 inline void
 195 FetchSeqUnit::squashAfterInst(DynInstPtr inst, int stage_num, unsigned tid)
 196 {
 197     // Squash In Pipeline Stage
 198     cpu->pipelineStage[stage_num]->squashDueToBranch(inst, tid);
 199
 200     // Squash inside current resource, so if there needs to be fetching on same cycle
 201     // the fetch information will be correct.
 202     // squash(inst, stage_num, inst->bdelaySeqNum, tid);
 203
 204     // Schedule Squash Through-out Resource Pool
 205     cpu->resPool->scheduleEvent((InOrderCPU::CPUEventType)ResourcePool::SquashAll, inst, 0);
 206 }
 207 void
 208 FetchSeqUnit::squash(DynInstPtr inst, int squash_stage,
 209                      InstSeqNum squash_seq_num, unsigned tid)
 210 {
 211     DPRINTF(InOrderFetchSeq, "[tid:%i]: Updating due to squash from stage %i.\n",
 212             tid, squash_stage);
 213
 214     InstSeqNum done_seq_num = inst->bdelaySeqNum;
 215     Addr new_PC = inst->readPredTarg();
 216
 217     if (squashSeqNum[tid] <= done_seq_num &&
 218         lastSquashCycle[tid] == curTick) {
 219         DPRINTF(InOrderFetchSeq, "[tid:%i]: Ignoring squash from stage %i, since"
 220                 "there is an outstanding squash that is older.\n",
 221                 tid, squash_stage);
 222     } else {
 223         squashSeqNum[tid] = done_seq_num;
 224         lastSquashCycle[tid] = curTick;
 225
 226         // If The very next instruction number is the done seq. num,
 227         // then we haven't seen the delay slot yet ... if it isn't
 228         // the last done_seq_num then this is the delay slot inst.
 229         if (cpu->nextInstSeqNum(tid) != done_seq_num &&
 230             !inst->procDelaySlotOnMispred) {
 231             delaySlotInfo[tid].numInsts = 0;
 232             delaySlotInfo[tid].targetReady = false;
 233
 234             // Reset PC
 235             PC[tid] = new_PC;
 236             nextPC[tid] = new_PC + instSize;
 237             nextNPC[tid] = new_PC + (2 * instSize);
 238
 239             DPRINTF(InOrderFetchSeq, "[tid:%i]: Setting PC to %08p.\n",
 240                     tid, PC[tid]);
 241         } else {
 242             delaySlotInfo[tid].numInsts = 1;
 243             delaySlotInfo[tid].targetReady = false;
 244             delaySlotInfo[tid].targetAddr = (inst->procDelaySlotOnMispred) ? inst->branchTarget() : new_PC;
 245
 246             // Reset PC to Delay Slot Instruction
 247             if (inst->procDelaySlotOnMispred) {
 248                 PC[tid] = new_PC;
 249                 nextPC[tid] = new_PC + instSize;
 250                 nextNPC[tid] = new_PC + (2 * instSize);
 251             }
 252
 253         }
 254
 255         // Unblock Any Stages Waiting for this information to be updated ...
 256         if (!pcValid[tid]) {
 257             cpu->pipelineStage[pcBlockStage[tid]]->toPrevStages->stageUnblock[pcBlockStage[tid]][tid] = true;
 258         }
 259
 260         pcValid[tid] = true;
 261     }
 262
 263     Resource::squash(inst, squash_stage, squash_seq_num, tid);
 264 }
 265
 266 FetchSeqUnit::FetchSeqEvent::FetchSeqEvent()
 267     : ResourceEvent()
 268 { }
 269
 270 void
 271 FetchSeqUnit::FetchSeqEvent::process()
 272 {
 273     FetchSeqUnit* fs_res = dynamic_cast<FetchSeqUnit*>(resource);
 274     assert(fs_res);
 275
 276     for (int i=0; i < MaxThreads; i++) {
 277         fs_res->PC[i] = fs_res->cpu->readPC(i);
 278         fs_res->nextPC[i] = fs_res->cpu->readNextPC(i);
 279         fs_res->nextNPC[i] = fs_res->cpu->readNextNPC(i);
 280         DPRINTF(InOrderFetchSeq, "[tid:%i]: Setting PC:%08p NPC:%08p NNPC:%08p.\n",
 281                 fs_res->PC[i], fs_res->nextPC[i], fs_res->nextNPC[i]);
 282
 283         fs_res->pcValid[i] = true;
 284     }
 285
 286     //cpu->fetchPriorityList.push_back(tid);
 287 }
 288
 289
 290 void
 291 FetchSeqUnit::activateThread(unsigned tid)
 292 {
 293     pcValid[tid] = true;
 294
 295     PC[tid] = cpu->readPC(tid);
 296     nextPC[tid] = cpu->readNextPC(tid);
 297     nextNPC[tid] = cpu->readNextNPC(tid);
 298
 299     cpu->fetchPriorityList.push_back(tid);
 300
 301     DPRINTF(InOrderFetchSeq, "[tid:%i]: Reading PC:%08p NPC:%08p NNPC:%08p.\n",
 302             tid, PC[tid], nextPC[tid], nextNPC[tid]);
 303 }
 304
 305 void
 306 FetchSeqUnit::deactivateThread(unsigned tid)
 307 {
 308     delaySlotInfo[tid].numInsts = 0;
 309     delaySlotInfo[tid].targetReady = false;
 310
 311     pcValid[tid] = false;
 312     pcBlockStage[tid] = 0;
 313
 314     squashSeqNum[tid] = (InstSeqNum)-1;
 315     lastSquashCycle[tid] = 0;
 316
 317     std::list<unsigned>::iterator thread_it = find(cpu->fetchPriorityList.begin(),
 318                                               cpu->fetchPriorityList.end(),
 319                                               tid);
 320
 321     if (thread_it != cpu->fetchPriorityList.end())
 322         cpu->fetchPriorityList.erase(thread_it);
 323 }