src/cpu/inorder/resources/fetch_seq_unit.cc

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #include "config/the_isa.hh"
  33 #include "cpu/inorder/resources/fetch_seq_unit.hh"
  34 #include "cpu/inorder/resource_pool.hh"
  35
  36 using namespace std;
  37 using namespace TheISA;
  38 using namespace ThePipeline;
  39
  40 FetchSeqUnit::FetchSeqUnit(std::string res_name, int res_id, int res_width,
  41                        int res_latency, InOrderCPU *_cpu, ThePipeline::Params *params)
  42     : Resource(res_name, res_id, res_width, res_latency, _cpu),
  43       instSize(sizeof(MachInst))
  44 {
  45     for (ThreadID tid = 0; tid < ThePipeline::MaxThreads; tid++) {
  46         delaySlotInfo[tid].numInsts = 0;
  47         delaySlotInfo[tid].targetReady = false;
  48
  49         pcValid[tid] = false;
  50         pcBlockStage[tid] = 0;
  51
  52         squashSeqNum[tid] = (InstSeqNum)-1;
  53         lastSquashCycle[tid] = 0;
  54     }
  55 }
  56
  57 void
  58 FetchSeqUnit::init()
  59 {
  60     resourceEvent = new FetchSeqEvent[width];
  61
  62     initSlots();
  63 }
  64
  65 void
  66 FetchSeqUnit::execute(int slot_num)
  67 {
  68     // After this is working, change this to a reinterpret cast
  69     // for performance considerations
  70     ResourceRequest* fs_req = reqMap[slot_num];
  71     DynInstPtr inst = fs_req->inst;
  72     ThreadID tid = inst->readTid();
  73     int stage_num = fs_req->getStageNum();
  74     int seq_num = inst->seqNum;
  75
  76     fs_req->fault = NoFault;
  77
  78     switch (fs_req->cmd)
  79     {
  80       case AssignNextPC:
  81         {
  82             if (pcValid[tid]) {
  83
  84                 if (delaySlotInfo[tid].targetReady &&
  85                     delaySlotInfo[tid].numInsts == 0) {
  86                     // Set PC to target
  87                     PC[tid] = delaySlotInfo[tid].targetAddr; //next_PC
  88                     nextPC[tid] = PC[tid] + instSize;        //next_NPC
  89                     nextNPC[tid] = PC[tid] + (2 * instSize);
  90
  91                     delaySlotInfo[tid].targetReady = false;
  92
  93                     DPRINTF(InOrderFetchSeq, "[tid:%i]: Setting PC to delay slot target\n",tid);
  94                 }
  95
  96                 inst->setPC(PC[tid]);
  97                 inst->setNextPC(PC[tid] + instSize);
  98                 inst->setNextNPC(PC[tid] + (instSize * 2));
  99
 100 #if ISA_HAS_DELAY_SLOT
 101                 inst->setPredTarg(inst->readNextNPC());
 102 #else
 103                 inst->setPredTarg(inst->readNextPC());
 104 #endif
 105                 inst->setMemAddr(PC[tid]);
 106                 inst->setSeqNum(cpu->getAndIncrementInstSeq(tid));
 107
 108                 DPRINTF(InOrderFetchSeq, "[tid:%i]: Assigning [sn:%i] to PC %08p, NPC %08p, NNPC %08p\n", tid,
 109                         inst->seqNum, inst->readPC(), inst->readNextPC(), inst->readNextNPC());
 110
 111                 if (delaySlotInfo[tid].numInsts > 0) {
 112                     --delaySlotInfo[tid].numInsts;
 113
 114                     // It's OK to set PC to target of branch
 115                     if (delaySlotInfo[tid].numInsts == 0) {
 116                         delaySlotInfo[tid].targetReady = true;
 117                     }
 118
 119                     DPRINTF(InOrderFetchSeq, "[tid:%i]: %i delay slot inst(s) left to"
 120                             " process.\n", tid, delaySlotInfo[tid].numInsts);
 121                 }
 122
 123                 PC[tid] = nextPC[tid];
 124                 nextPC[tid] = nextNPC[tid];
 125                 nextNPC[tid] += instSize;
 126
 127                 fs_req->done();
 128             } else {
 129                 DPRINTF(InOrderStall, "STALL: [tid:%i]: NPC not valid\n", tid);
 130                 fs_req->setCompleted(false);
 131             }
 132         }
 133         break;
 134
 135       case UpdateTargetPC:
 136         {
 137             if (inst->isControl()) {
 138                 // If it's a return, then we must wait for resolved address.
 139                 if (inst->isReturn() && !inst->predTaken()) {
 140                     cpu->pipelineStage[stage_num]->toPrevStages->stageBlock[stage_num][tid] = true;
 141                     pcValid[tid] = false;
 142                     pcBlockStage[tid] = stage_num;
 143                 } else if (inst->isCondDelaySlot() && !inst->predTaken()) {
 144                 // Not-Taken AND Conditional Control
 145                     DPRINTF(InOrderFetchSeq, "[tid:%i]: [sn:%i]: [PC:%08p] Predicted Not-Taken Cond. "
 146                             "Delay inst. Skipping delay slot and  Updating PC to %08p\n",
 147                             tid, inst->seqNum, inst->readPC(), inst->readPredTarg());
 148
 149                     DPRINTF(InOrderFetchSeq, "[tid:%i] Setting up squash to start from stage %i, after [sn:%i].\n",
 150                             tid, stage_num, seq_num);
 151
 152                     inst->bdelaySeqNum = seq_num;
 153                     inst->squashingStage = stage_num;
 154
 155                     squashAfterInst(inst, stage_num, tid);
 156                 } else if (!inst->isCondDelaySlot() && !inst->predTaken()) {
 157                     // Not-Taken Control
 158                     DPRINTF(InOrderFetchSeq, "[tid:%i]: [sn:%i]: Predicted Not-Taken Control "
 159                             "inst. updating PC to %08p\n", tid, inst->seqNum,
 160                             inst->readNextPC());
 161 #if ISA_HAS_DELAY_SLOT
 162                     ++delaySlotInfo[tid].numInsts;
 163                     delaySlotInfo[tid].targetReady = false;
 164                     delaySlotInfo[tid].targetAddr = inst->readNextNPC();
 165 #else
 166                     assert(delaySlotInfo[tid].numInsts == 0);
 167 #endif
 168                 } else if (inst->predTaken()) {
 169                     // Taken Control
 170 #if ISA_HAS_DELAY_SLOT
 171                     ++delaySlotInfo[tid].numInsts;
 172                     delaySlotInfo[tid].targetReady = false;
 173                     delaySlotInfo[tid].targetAddr = inst->readPredTarg();
 174
 175                     DPRINTF(InOrderFetchSeq, "[tid:%i]: [sn:%i] Updating delay slot target "
 176                             "to PC %08p\n", tid, inst->seqNum, inst->readPredTarg());
 177                     inst->bdelaySeqNum = seq_num + 1;
 178 #else
 179                     inst->bdelaySeqNum = seq_num;
 180                     assert(delaySlotInfo[tid].numInsts == 0);
 181 #endif
 182
 183                     inst->squashingStage = stage_num;
 184
 185                     DPRINTF(InOrderFetchSeq, "[tid:%i] Setting up squash to start from stage %i, after [sn:%i].\n",
 186                             tid, stage_num, inst->bdelaySeqNum);
 187
 188                     // Do Squashing
 189                     squashAfterInst(inst, stage_num, tid);
 190                 }
 191             } else {
 192                 DPRINTF(InOrderFetchSeq, "[tid:%i]: [sn:%i]: Ignoring branch target update "
 193                         "since then is not a control instruction.\n", tid, inst->seqNum);
 194             }
 195
 196             fs_req->done();
 197         }
 198         break;
 199
 200       default:
 201         fatal("Unrecognized command to %s", resName);
 202     }
 203 }
 204
 205 inline void
 206 FetchSeqUnit::squashAfterInst(DynInstPtr inst, int stage_num, ThreadID tid)
 207 {
 208     // Squash In Pipeline Stage
 209     cpu->pipelineStage[stage_num]->squashDueToBranch(inst, tid);
 210
 211     // Squash inside current resource, so if there needs to be fetching on same cycle
 212     // the fetch information will be correct.
 213     // squash(inst, stage_num, inst->bdelaySeqNum, tid);
 214
 215     // Schedule Squash Through-out Resource Pool
 216     cpu->resPool->scheduleEvent((InOrderCPU::CPUEventType)ResourcePool::SquashAll, inst, 0);
 217 }
 218 void
 219 FetchSeqUnit::squash(DynInstPtr inst, int squash_stage,
 220                      InstSeqNum squash_seq_num, ThreadID tid)
 221 {
 222     DPRINTF(InOrderFetchSeq, "[tid:%i]: Updating due to squash from stage %i.\n",
 223             tid, squash_stage);
 224
 225     InstSeqNum done_seq_num = inst->bdelaySeqNum;
 226     Addr new_PC = inst->readPredTarg();
 227
 228     if (squashSeqNum[tid] <= done_seq_num &&
 229         lastSquashCycle[tid] == curTick) {
 230         DPRINTF(InOrderFetchSeq, "[tid:%i]: Ignoring squash from stage %i, since"
 231                 "there is an outstanding squash that is older.\n",
 232                 tid, squash_stage);
 233     } else {
 234         squashSeqNum[tid] = done_seq_num;
 235         lastSquashCycle[tid] = curTick;
 236
 237         // If The very next instruction number is the done seq. num,
 238         // then we haven't seen the delay slot yet ... if it isn't
 239         // the last done_seq_num then this is the delay slot inst.
 240         if (cpu->nextInstSeqNum(tid) != done_seq_num &&
 241             !inst->procDelaySlotOnMispred) {
 242             delaySlotInfo[tid].numInsts = 0;
 243             delaySlotInfo[tid].targetReady = false;
 244
 245             // Reset PC
 246             PC[tid] = new_PC;
 247             nextPC[tid] = new_PC + instSize;
 248             nextNPC[tid] = new_PC + (2 * instSize);
 249
 250             DPRINTF(InOrderFetchSeq, "[tid:%i]: Setting PC to %08p.\n",
 251                     tid, PC[tid]);
 252         } else {
 253 #if !ISA_HAS_DELAY_SLOT
 254             assert(0);
 255 #endif
 256
 257             delaySlotInfo[tid].numInsts = 1;
 258             delaySlotInfo[tid].targetReady = false;
 259             delaySlotInfo[tid].targetAddr = (inst->procDelaySlotOnMispred) ? inst->branchTarget() : new_PC;
 260
 261             // Reset PC to Delay Slot Instruction
 262             if (inst->procDelaySlotOnMispred) {
 263                 PC[tid] = new_PC;
 264                 nextPC[tid] = new_PC + instSize;
 265                 nextNPC[tid] = new_PC + (2 * instSize);
 266             }
 267
 268         }
 269
 270         // Unblock Any Stages Waiting for this information to be updated ...
 271         if (!pcValid[tid]) {
 272             cpu->pipelineStage[pcBlockStage[tid]]->toPrevStages->stageUnblock[pcBlockStage[tid]][tid] = true;
 273         }
 274
 275         pcValid[tid] = true;
 276     }
 277
 278     Resource::squash(inst, squash_stage, squash_seq_num, tid);
 279 }
 280
 281 FetchSeqUnit::FetchSeqEvent::FetchSeqEvent()
 282     : ResourceEvent()
 283 { }
 284
 285 void
 286 FetchSeqUnit::FetchSeqEvent::process()
 287 {
 288     FetchSeqUnit* fs_res = dynamic_cast<FetchSeqUnit*>(resource);
 289     assert(fs_res);
 290
 291     for (int i=0; i < MaxThreads; i++) {
 292         fs_res->PC[i] = fs_res->cpu->readPC(i);
 293         fs_res->nextPC[i] = fs_res->cpu->readNextPC(i);
 294         fs_res->nextNPC[i] = fs_res->cpu->readNextNPC(i);
 295         DPRINTF(InOrderFetchSeq, "[tid:%i]: Setting PC:%08p NPC:%08p NNPC:%08p.\n",
 296                 fs_res->PC[i], fs_res->nextPC[i], fs_res->nextNPC[i]);
 297
 298         fs_res->pcValid[i] = true;
 299     }
 300
 301     //cpu->fetchPriorityList.push_back(tid);
 302 }
 303
 304
 305 void
 306 FetchSeqUnit::activateThread(ThreadID tid)
 307 {
 308     pcValid[tid] = true;
 309
 310     PC[tid] = cpu->readPC(tid);
 311     nextPC[tid] = cpu->readNextPC(tid);
 312     nextNPC[tid] = cpu->readNextNPC(tid);
 313
 314     cpu->fetchPriorityList.push_back(tid);
 315
 316     DPRINTF(InOrderFetchSeq, "[tid:%i]: Reading PC:%08p NPC:%08p NNPC:%08p.\n",
 317             tid, PC[tid], nextPC[tid], nextNPC[tid]);
 318 }
 319
 320 void
 321 FetchSeqUnit::deactivateThread(ThreadID tid)
 322 {
 323     delaySlotInfo[tid].numInsts = 0;
 324     delaySlotInfo[tid].targetReady = false;
 325
 326     pcValid[tid] = false;
 327     pcBlockStage[tid] = 0;
 328
 329     squashSeqNum[tid] = (InstSeqNum)-1;
 330     lastSquashCycle[tid] = 0;
 331
 332     list<ThreadID>::iterator thread_it = find(cpu->fetchPriorityList.begin(),
 333                                               cpu->fetchPriorityList.end(),
 334                                               tid);
 335
 336     if (thread_it != cpu->fetchPriorityList.end())
 337         cpu->fetchPriorityList.erase(thread_it);
 338 }
 339
 340 void
 341 FetchSeqUnit::suspendThread(ThreadID tid)
 342 {
 343     deactivateThread(tid);
 344 }
 345
 346 void
 347 FetchSeqUnit::updateAfterContextSwitch(DynInstPtr inst, ThreadID tid)
 348 {
 349     pcValid[tid] = true;
 350
 351     PC[tid] = inst->readNextPC();
 352     nextPC[tid] = inst->readNextNPC();
 353     nextNPC[tid] = inst->readNextNPC() + instSize;
 354
 355
 356     DPRINTF(InOrderFetchSeq, "[tid:%i]: Updating  PC:%08p NPC:%08p NNPC:%08p.\n",
 357             tid, PC[tid], nextPC[tid], nextNPC[tid]);
 358 }