src/cpu/inorder/resources/fetch_seq_unit.cc

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #include "config/the_isa.hh"
  33 #include "cpu/inorder/resources/fetch_seq_unit.hh"
  34 #include "cpu/inorder/resource_pool.hh"
  35 #include "debug/InOrderFetchSeq.hh"
  36 #include "debug/InOrderStall.hh"
  37
  38 using namespace std;
  39 using namespace TheISA;
  40 using namespace ThePipeline;
  41
  42 FetchSeqUnit::FetchSeqUnit(std::string res_name, int res_id, int res_width,
  43                            int res_latency, InOrderCPU *_cpu,
  44                            ThePipeline::Params *params)
  45     : Resource(res_name, res_id, res_width, res_latency, _cpu),
  46       instSize(sizeof(MachInst))
  47 {
  48     for (ThreadID tid = 0; tid < ThePipeline::MaxThreads; tid++) {
  49         pcValid[tid] = false;
  50         pcBlockStage[tid] = 0;
  51
  52         squashSeqNum[tid] = (InstSeqNum)-1;
  53         lastSquashCycle[tid] = 0;
  54     }
  55 }
  56
  57 FetchSeqUnit::~FetchSeqUnit()
  58 {
  59     delete [] resourceEvent;
  60 }
  61
  62 void
  63 FetchSeqUnit::init()
  64 {
  65     resourceEvent = new FetchSeqEvent[width];
  66
  67     for (int i = 0; i < width; i++) {
  68         reqs[i] = new ResourceRequest(this);
  69     }
  70
  71     initSlots();
  72 }
  73
  74 void
  75 FetchSeqUnit::execute(int slot_num)
  76 {
  77     ResourceRequest* fs_req = reqs[slot_num];
  78     DynInstPtr inst = fs_req->inst;
  79     ThreadID tid = inst->readTid();
  80     int stage_num = fs_req->getStageNum();
  81     InstSeqNum seq_num = inst->seqNum;
  82
  83     DPRINTF(InOrderFetchSeq, "[tid:%i]: Current PC is %s\n", tid,
  84             pc[tid]);
  85
  86     switch (fs_req->cmd)
  87     {
  88       case AssignNextPC:
  89         {
  90             if (pcValid[tid]) {
  91                 inst->pcState(pc[tid]);
  92                 inst->setMemAddr(pc[tid].instAddr());
  93
  94                 // Advance to next PC (typically PC + 4)
  95                 pc[tid].advance();
  96
  97                 inst->setSeqNum(cpu->getAndIncrementInstSeq(tid));
  98
  99                 DPRINTF(InOrderFetchSeq, "[tid:%i]: Assigning [sn:%i] to "
 100                         "PC %s\n", tid, inst->seqNum, inst->pcState());
 101
 102                 fs_req->done();
 103             } else {
 104                 DPRINTF(InOrderStall, "STALL: [tid:%i]: NPC not valid\n", tid);
 105                 fs_req->done(false);
 106             }
 107         }
 108         break;
 109
 110       case UpdateTargetPC:
 111         {
 112             if (inst->isControl()) {
 113                 // If it's a return, then we must wait for resolved address.
 114                 // The Predictor will mark a return a false as "not taken"
 115                 // if there is no RAS entry
 116                 if (inst->isReturn() && !inst->predTaken()) {
 117                     cpu->pipelineStage[stage_num]->
 118                         toPrevStages->stageBlock[stage_num][tid] = true;
 119                     pcValid[tid] = false;
 120                     pcBlockStage[tid] = stage_num;
 121                 } else if (inst->isCondDelaySlot() && !inst->predTaken()) {
 122                     assert(0 && "Not Handling Conditional Delay Slot");
 123                     // Not-Taken AND Conditional Control
 124                     DPRINTF(InOrderFetchSeq, "[tid:%i]: [sn:%i]: [PC:%s] "
 125                             "Predicted Not-Taken Cond. Delay inst. Skipping "
 126                             "delay slot and  Updating PC to %s\n",
 127                             tid, inst->seqNum, inst->pcState(),
 128                             inst->readPredTarg());
 129
 130                     DPRINTF(InOrderFetchSeq, "[tid:%i] Setting up squash to "
 131                             "start from stage %i, after [sn:%i].\n", tid,
 132                             stage_num, seq_num);
 133
 134                     inst->bdelaySeqNum = seq_num;
 135                     inst->squashingStage = stage_num;
 136
 137                     squashAfterInst(inst, stage_num, tid);
 138                 } else if (!inst->isCondDelaySlot() && !inst->predTaken()) {
 139                     // Not-Taken Control
 140                     DPRINTF(InOrderFetchSeq, "[tid:%i]: [sn:%i]: Predicted "
 141                             "Not-Taken Control "
 142                             "inst. updating PC to %s\n", tid, inst->seqNum,
 143                             inst->readPredTarg());
 144                 } else if (inst->predTaken()) {
 145                     // Taken Control
 146 #if ISA_HAS_DELAY_SLOT
 147                     DPRINTF(InOrderFetchSeq, "[tid:%i]: [sn:%i] Updating delay"
 148                             " slot target to PC %s\n", tid, inst->seqNum,
 149                             inst->readPredTarg());
 150                     inst->bdelaySeqNum = seq_num + 1;
 151 #else
 152                     inst->bdelaySeqNum = seq_num;
 153 #endif
 154
 155                     inst->squashingStage = stage_num;
 156                     DPRINTF(InOrderFetchSeq, "[tid:%i] Setting up squash to "
 157                             "start from stage %i, after [sn:%i].\n",
 158                             tid, stage_num, inst->bdelaySeqNum);
 159
 160                     // Do Squashing
 161                     squashAfterInst(inst, stage_num, tid);
 162                 }
 163             } else {
 164                 DPRINTF(InOrderFetchSeq, "[tid:%i]: [sn:%i]: Ignoring branch "
 165                         "target update since then is not a control "
 166                         "instruction.\n", tid, inst->seqNum);
 167             }
 168
 169             fs_req->done();
 170         }
 171         break;
 172
 173       default:
 174         fatal("Unrecognized command to %s", resName);
 175     }
 176 }
 177
 178 inline void
 179 FetchSeqUnit::squashAfterInst(DynInstPtr inst, int stage_num, ThreadID tid)
 180 {
 181     // Squash In Pipeline Stage
 182     cpu->pipelineStage[stage_num]->squashDueToBranch(inst, tid);
 183
 184     // Schedule Squash Through-out Resource Pool
 185     cpu->resPool->scheduleEvent(
 186             (InOrderCPU::CPUEventType)ResourcePool::SquashAll, inst, 0);
 187 }
 188
 189 void
 190 FetchSeqUnit::squash(DynInstPtr inst, int squash_stage,
 191                      InstSeqNum squash_seq_num, ThreadID tid)
 192 {
 193     DPRINTF(InOrderFetchSeq, "[tid:%i]: Updating due to squash from stage %i."
 194             "\n", tid, squash_stage);
 195
 196     InstSeqNum done_seq_num = inst->bdelaySeqNum;
 197
 198     // Handles the case where we are squashing because of something that is
 199     // not a branch...like a memory stall
 200     TheISA::PCState newPC;
 201     if (inst->isControl()) {
 202         newPC = inst->readPredTarg();
 203     } else {
 204         TheISA::PCState thisPC = inst->pcState();
 205         assert(inst->staticInst);
 206         advancePC(thisPC, inst->staticInst);
 207         newPC = thisPC;
 208     }
 209
 210     if (squashSeqNum[tid] <= done_seq_num &&
 211         lastSquashCycle[tid] == curTick()) {
 212         DPRINTF(InOrderFetchSeq, "[tid:%i]: Ignoring squash from stage %i, "
 213                 "since there is an outstanding squash that is older.\n",
 214                 tid, squash_stage);
 215     } else {
 216         squashSeqNum[tid] = done_seq_num;
 217         lastSquashCycle[tid] = curTick();
 218
 219         if (inst->isControl()) {
 220             // If the next inst. num is greater than done seq num,
 221             // then that means we have seen the delay slot
 222             assert(cpu->nextInstSeqNum(tid) >= done_seq_num);
 223             if (cpu->nextInstSeqNum(tid) > done_seq_num) {
 224                 // Reset PC
 225                 pc[tid] = newPC;
 226
 227 #if ISA_HAS_DELAY_SLOT
 228                 // The Pred. Target will be (NPC, NNPC, NNPC+4)
 229                 // so since we already saw the NPC (i.e. delay slot)
 230                 // advance one more to get (NNPC, NNPC+4, NNPC+8)
 231                 TheISA::advancePC(pc[tid], inst->staticInst);
 232 #endif
 233
 234                 DPRINTF(InOrderFetchSeq, "[tid:%i]: Setting PC to %s.\n",
 235                         tid, newPC);
 236             } else {
 237                 // If The very next instruction number that needs to be given
 238                 // out by the CPU is the done seq. num, then we haven't seen
 239                 // the delay slot instruction yet.
 240                 assert(ISA_HAS_DELAY_SLOT);
 241                 pc[tid] =  newPC;
 242             }
 243         } else {
 244             pc[tid] = newPC;
 245         }
 246
 247         // Unblock Any Stages Waiting for this information to be updated ...
 248         if (!pcValid[tid]) {
 249             cpu->pipelineStage[pcBlockStage[tid]]->
 250                 toPrevStages->stageUnblock[pcBlockStage[tid]][tid] = true;
 251         }
 252
 253         pcValid[tid] = true;
 254     }
 255
 256     Resource::squash(inst, squash_stage, squash_seq_num, tid);
 257 }
 258
 259 FetchSeqUnit::FetchSeqEvent::FetchSeqEvent()
 260     : ResourceEvent()
 261 { }
 262
 263 void
 264 FetchSeqUnit::FetchSeqEvent::process()
 265 {
 266     FetchSeqUnit* fs_res = dynamic_cast<FetchSeqUnit*>(resource);
 267     assert(fs_res);
 268
 269     for (int i = 0; i < MaxThreads; i++) {
 270         fs_res->pc[i] = fs_res->cpu->pcState(i);
 271         DPRINTF(InOrderFetchSeq, "[tid:%i]: Setting PC: %s.\n",
 272                 fs_res->pc[i]);
 273
 274         fs_res->pcValid[i] = true;
 275     }
 276 }
 277
 278
 279 void
 280 FetchSeqUnit::activateThread(ThreadID tid)
 281 {
 282     pcValid[tid] = true;
 283
 284     pc[tid] = cpu->pcState(tid);
 285
 286     cpu->fetchPriorityList.push_back(tid);
 287
 288     DPRINTF(InOrderFetchSeq, "[tid:%i]: Reading PC: %s.\n",
 289             tid, pc[tid]);
 290 }
 291
 292 void
 293 FetchSeqUnit::deactivateThread(ThreadID tid)
 294 {
 295     pcValid[tid] = false;
 296     pcBlockStage[tid] = 0;
 297
 298     squashSeqNum[tid] = (InstSeqNum)-1;
 299     lastSquashCycle[tid] = 0;
 300
 301     list<ThreadID>::iterator thread_it = find(cpu->fetchPriorityList.begin(),
 302                                               cpu->fetchPriorityList.end(),
 303                                               tid);
 304
 305     if (thread_it != cpu->fetchPriorityList.end())
 306         cpu->fetchPriorityList.erase(thread_it);
 307 }
 308
 309 void
 310 FetchSeqUnit::suspendThread(ThreadID tid)
 311 {
 312     deactivateThread(tid);
 313 }
 314
 315 void
 316 FetchSeqUnit::updateAfterContextSwitch(DynInstPtr inst, ThreadID tid)
 317 {
 318     pcValid[tid] = true;
 319
 320     if (cpu->thread[tid]->lastGradIsBranch) {
 321         /** This function assumes that the instruction causing the context
 322          *  switch was right after the branch. Thus, if it's not, then
 323          *  we are updating incorrectly here
 324          */
 325         assert(cpu->nextInstAddr(tid) == inst->instAddr());
 326         pc[tid] = cpu->thread[tid]->lastBranchPC;
 327     } else {
 328         pc[tid] = inst->pcState();
 329     }
 330     assert(inst->staticInst);
 331     advancePC(pc[tid], inst->staticInst);
 332
 333     DPRINTF(InOrderFetchSeq, "[tid:%i]: Updating PCs due to Context Switch."
 334             "Assigning  PC: %s.\n", tid, pc[tid]);
 335 }