src/cpu/inorder/resources/fetch_seq_unit.cc

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #include "config/the_isa.hh"
  33 #include "cpu/inorder/resources/fetch_seq_unit.hh"
  34 #include "cpu/inorder/resource_pool.hh"
  35 #include "debug/InOrderFetchSeq.hh"
  36 #include "debug/InOrderStall.hh"
  37
  38 using namespace std;
  39 using namespace TheISA;
  40 using namespace ThePipeline;
  41
  42 FetchSeqUnit::FetchSeqUnit(std::string res_name, int res_id, int res_width,
  43                            int res_latency, InOrderCPU *_cpu,
  44                            ThePipeline::Params *params)
  45     : Resource(res_name, res_id, res_width, res_latency, _cpu),
  46       instSize(sizeof(MachInst))
  47 {
  48     for (ThreadID tid = 0; tid < ThePipeline::MaxThreads; tid++) {
  49         pcValid[tid] = false;
  50         pcBlockStage[tid] = 0;
  51
  52         squashSeqNum[tid] = (InstSeqNum)-1;
  53         lastSquashCycle[tid] = 0;
  54     }
  55 }
  56
  57 FetchSeqUnit::~FetchSeqUnit()
  58 {
  59     delete [] resourceEvent;
  60 }
  61
  62 void
  63 FetchSeqUnit::init()
  64 {
  65     resourceEvent = new FetchSeqEvent[width];
  66
  67     for (int i = 0; i < width; i++) {
  68         reqs[i] = new ResourceRequest(this);
  69     }
  70
  71     initSlots();
  72 }
  73
  74 void
  75 FetchSeqUnit::execute(int slot_num)
  76 {
  77     ResourceRequest* fs_req = reqs[slot_num];
  78     DynInstPtr inst = fs_req->inst;
  79     ThreadID tid = inst->readTid();
  80     int stage_num = fs_req->getStageNum();
  81     InstSeqNum seq_num = inst->seqNum;
  82
  83     DPRINTF(InOrderFetchSeq, "[tid:%i]: Current PC is %s\n", tid,
  84             pc[tid]);
  85
  86     switch (fs_req->cmd)
  87     {
  88       case AssignNextPC:
  89         {
  90             if (pcValid[tid]) {
  91                 inst->pcState(pc[tid]);
  92                 inst->setMemAddr(pc[tid].instAddr());
  93
  94                 // Advance to next PC (typically PC + 4)
  95                 pc[tid].advance();
  96
  97                 inst->setSeqNum(cpu->getAndIncrementInstSeq(tid));
  98
  99                 DPRINTF(InOrderFetchSeq, "[tid:%i]: Assigning [sn:%i] to "
 100                         "PC %s\n", tid, inst->seqNum, inst->pcState());
 101
 102                 fs_req->done();
 103             } else {
 104                 DPRINTF(InOrderStall, "STALL: [tid:%i]: NPC not valid\n", tid);
 105                 fs_req->done(false);
 106             }
 107         }
 108         break;
 109
 110       case UpdateTargetPC:
 111         {
 112             if (inst->isControl()) {
 113                 // If it's a return, then we must wait for resolved address.
 114                 if (inst->isReturn() && !inst->predTaken()) {
 115                     cpu->pipelineStage[stage_num]->
 116                         toPrevStages->stageBlock[stage_num][tid] = true;
 117                     pcValid[tid] = false;
 118                     pcBlockStage[tid] = stage_num;
 119                 } else if (inst->isCondDelaySlot() && !inst->predTaken()) {
 120                 // Not-Taken AND Conditional Control
 121                     DPRINTF(InOrderFetchSeq, "[tid:%i]: [sn:%i]: [PC:%s] "
 122                             "Predicted Not-Taken Cond. Delay inst. Skipping "
 123                             "delay slot and  Updating PC to %s\n",
 124                             tid, inst->seqNum, inst->pcState(),
 125                             inst->readPredTarg());
 126
 127                     DPRINTF(InOrderFetchSeq, "[tid:%i] Setting up squash to "
 128                             "start from stage %i, after [sn:%i].\n", tid,
 129                             stage_num, seq_num);
 130
 131                     inst->bdelaySeqNum = seq_num;
 132                     inst->squashingStage = stage_num;
 133
 134                     squashAfterInst(inst, stage_num, tid);
 135                 } else if (!inst->isCondDelaySlot() && !inst->predTaken()) {
 136                     // Not-Taken Control
 137                     DPRINTF(InOrderFetchSeq, "[tid:%i]: [sn:%i]: Predicted "
 138                             "Not-Taken Control "
 139                             "inst. updating PC to %s\n", tid, inst->seqNum,
 140                             inst->readPredTarg());
 141 #if ISA_HAS_DELAY_SLOT
 142                     pc[tid] = inst->pcState();
 143                     advancePC(pc[tid], inst->staticInst);
 144 #endif
 145                 } else if (inst->predTaken()) {
 146                     // Taken Control
 147 #if ISA_HAS_DELAY_SLOT
 148                     pc[tid] = inst->readPredTarg();
 149
 150                     DPRINTF(InOrderFetchSeq, "[tid:%i]: [sn:%i] Updating delay"
 151                             " slot target to PC %s\n", tid, inst->seqNum,
 152                             inst->readPredTarg());
 153                     inst->bdelaySeqNum = seq_num + 1;
 154 #else
 155                     inst->bdelaySeqNum = seq_num;
 156 #endif
 157
 158                     inst->squashingStage = stage_num;
 159                     DPRINTF(InOrderFetchSeq, "[tid:%i] Setting up squash to "
 160                             "start from stage %i, after [sn:%i].\n",
 161                             tid, stage_num, inst->bdelaySeqNum);
 162
 163                     // Do Squashing
 164                     squashAfterInst(inst, stage_num, tid);
 165                 }
 166             } else {
 167                 DPRINTF(InOrderFetchSeq, "[tid:%i]: [sn:%i]: Ignoring branch "
 168                         "target update since then is not a control "
 169                         "instruction.\n", tid, inst->seqNum);
 170             }
 171
 172             fs_req->done();
 173         }
 174         break;
 175
 176       default:
 177         fatal("Unrecognized command to %s", resName);
 178     }
 179 }
 180
 181 inline void
 182 FetchSeqUnit::squashAfterInst(DynInstPtr inst, int stage_num, ThreadID tid)
 183 {
 184     // Squash In Pipeline Stage
 185     cpu->pipelineStage[stage_num]->squashDueToBranch(inst, tid);
 186
 187     // Squash inside current resource, so if there needs to be fetching on
 188     // same cycle the fetch information will be correct.
 189
 190     // Schedule Squash Through-out Resource Pool
 191     cpu->resPool->scheduleEvent(
 192             (InOrderCPU::CPUEventType)ResourcePool::SquashAll, inst, 0);
 193 }
 194
 195 void
 196 FetchSeqUnit::squash(DynInstPtr inst, int squash_stage,
 197                      InstSeqNum squash_seq_num, ThreadID tid)
 198 {
 199     DPRINTF(InOrderFetchSeq, "[tid:%i]: Updating due to squash from stage %i."
 200             "\n", tid, squash_stage);
 201
 202     InstSeqNum done_seq_num = inst->bdelaySeqNum;
 203
 204     // Handles the case where we are squashing because of something that is
 205     // not a branch...like a memory stall
 206     TheISA::PCState newPC;
 207     if (inst->isControl()) {
 208         newPC = inst->readPredTarg();
 209     } else {
 210         TheISA::PCState thisPC = inst->pcState();
 211         assert(inst->staticInst);
 212         advancePC(thisPC, inst->staticInst);
 213         newPC = thisPC;
 214     }
 215
 216     if (squashSeqNum[tid] <= done_seq_num &&
 217         lastSquashCycle[tid] == curTick()) {
 218         DPRINTF(InOrderFetchSeq, "[tid:%i]: Ignoring squash from stage %i, "
 219                 "since there is an outstanding squash that is older.\n",
 220                 tid, squash_stage);
 221     } else {
 222         squashSeqNum[tid] = done_seq_num;
 223         lastSquashCycle[tid] = curTick();
 224
 225         // If The very next instruction number is the done seq. num,
 226         // then we haven't seen the delay slot yet ... if it isn't
 227         // the last done_seq_num then this is the delay slot inst.
 228         if (cpu->nextInstSeqNum(tid) != done_seq_num &&
 229             !inst->procDelaySlotOnMispred) {
 230
 231             // Reset PC
 232             pc[tid] = newPC;
 233 #if ISA_HAS_DELAY_SLOT
 234             TheISA::advancePC(pc[tid], inst->staticInst);
 235 #endif
 236
 237             DPRINTF(InOrderFetchSeq, "[tid:%i]: Setting PC to %s.\n",
 238                     tid, newPC);
 239         } else {
 240             assert(ISA_HAS_DELAY_SLOT);
 241
 242             pc[tid] = (inst->procDelaySlotOnMispred) ?
 243                 inst->branchTarget() : newPC;
 244
 245             // Reset PC to Delay Slot Instruction
 246             if (inst->procDelaySlotOnMispred) {
 247                 // Reset PC
 248                 pc[tid] = newPC;
 249             }
 250
 251         }
 252
 253         // Unblock Any Stages Waiting for this information to be updated ...
 254         if (!pcValid[tid]) {
 255             cpu->pipelineStage[pcBlockStage[tid]]->
 256                 toPrevStages->stageUnblock[pcBlockStage[tid]][tid] = true;
 257         }
 258
 259         pcValid[tid] = true;
 260     }
 261
 262     Resource::squash(inst, squash_stage, squash_seq_num, tid);
 263 }
 264
 265 FetchSeqUnit::FetchSeqEvent::FetchSeqEvent()
 266     : ResourceEvent()
 267 { }
 268
 269 void
 270 FetchSeqUnit::FetchSeqEvent::process()
 271 {
 272     FetchSeqUnit* fs_res = dynamic_cast<FetchSeqUnit*>(resource);
 273     assert(fs_res);
 274
 275     for (int i = 0; i < MaxThreads; i++) {
 276         fs_res->pc[i] = fs_res->cpu->pcState(i);
 277         DPRINTF(InOrderFetchSeq, "[tid:%i]: Setting PC: %s.\n",
 278                 fs_res->pc[i]);
 279
 280         fs_res->pcValid[i] = true;
 281     }
 282 }
 283
 284
 285 void
 286 FetchSeqUnit::activateThread(ThreadID tid)
 287 {
 288     pcValid[tid] = true;
 289
 290     pc[tid] = cpu->pcState(tid);
 291
 292     cpu->fetchPriorityList.push_back(tid);
 293
 294     DPRINTF(InOrderFetchSeq, "[tid:%i]: Reading PC: %s.\n",
 295             tid, pc[tid]);
 296 }
 297
 298 void
 299 FetchSeqUnit::deactivateThread(ThreadID tid)
 300 {
 301     pcValid[tid] = false;
 302     pcBlockStage[tid] = 0;
 303
 304     squashSeqNum[tid] = (InstSeqNum)-1;
 305     lastSquashCycle[tid] = 0;
 306
 307     list<ThreadID>::iterator thread_it = find(cpu->fetchPriorityList.begin(),
 308                                               cpu->fetchPriorityList.end(),
 309                                               tid);
 310
 311     if (thread_it != cpu->fetchPriorityList.end())
 312         cpu->fetchPriorityList.erase(thread_it);
 313 }
 314
 315 void
 316 FetchSeqUnit::suspendThread(ThreadID tid)
 317 {
 318     deactivateThread(tid);
 319 }
 320
 321 void
 322 FetchSeqUnit::updateAfterContextSwitch(DynInstPtr inst, ThreadID tid)
 323 {
 324     pcValid[tid] = true;
 325
 326     if (cpu->thread[tid]->lastGradIsBranch) {
 327         /** This function assumes that the instruction causing the context
 328          *  switch was right after the branch. Thus, if it's not, then
 329          *  we are updating incorrectly here
 330          */
 331         assert(cpu->nextInstAddr(tid) == inst->instAddr());
 332         pc[tid] = cpu->thread[tid]->lastBranchPC;
 333     } else {
 334         pc[tid] = inst->pcState();
 335     }
 336     assert(inst->staticInst);
 337     advancePC(pc[tid], inst->staticInst);
 338
 339     DPRINTF(InOrderFetchSeq, "[tid:%i]: Updating PCs due to Context Switch."
 340             "Assigning  PC: %s.\n", tid, pc[tid]);
 341 }