src/cpu/inorder/resources/fetch_seq_unit.cc

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #include "config/the_isa.hh"
  33 #include "cpu/inorder/resources/fetch_seq_unit.hh"
  34 #include "cpu/inorder/resource_pool.hh"
  35
  36 using namespace std;
  37 using namespace TheISA;
  38 using namespace ThePipeline;
  39
  40 FetchSeqUnit::FetchSeqUnit(std::string res_name, int res_id, int res_width,
  41                            int res_latency, InOrderCPU *_cpu,
  42                            ThePipeline::Params *params)
  43     : Resource(res_name, res_id, res_width, res_latency, _cpu),
  44       instSize(sizeof(MachInst))
  45 {
  46     for (ThreadID tid = 0; tid < ThePipeline::MaxThreads; tid++) {
  47         delaySlotInfo[tid].numInsts = 0;
  48         delaySlotInfo[tid].targetReady = false;
  49
  50         pcValid[tid] = false;
  51         pcBlockStage[tid] = 0;
  52
  53         squashSeqNum[tid] = (InstSeqNum)-1;
  54         lastSquashCycle[tid] = 0;
  55     }
  56 }
  57
  58 FetchSeqUnit::~FetchSeqUnit()
  59 {
  60     delete [] resourceEvent;
  61 }
  62
  63 void
  64 FetchSeqUnit::init()
  65 {
  66     resourceEvent = new FetchSeqEvent[width];
  67
  68     initSlots();
  69 }
  70
  71 void
  72 FetchSeqUnit::execute(int slot_num)
  73 {
  74     // After this is working, change this to a reinterpret cast
  75     // for performance considerations
  76     ResourceRequest* fs_req = reqMap[slot_num];
  77     DynInstPtr inst = fs_req->inst;
  78     ThreadID tid = inst->readTid();
  79     int stage_num = fs_req->getStageNum();
  80     int seq_num = inst->seqNum;
  81
  82     fs_req->fault = NoFault;
  83
  84     switch (fs_req->cmd)
  85     {
  86       case AssignNextPC:
  87         {
  88             if (pcValid[tid]) {
  89
  90                 if (delaySlotInfo[tid].targetReady &&
  91                     delaySlotInfo[tid].numInsts == 0) {
  92                     // Set PC to target
  93                     PC[tid] = delaySlotInfo[tid].targetAddr; //next_PC
  94                     nextPC[tid] = PC[tid] + instSize;        //next_NPC
  95                     nextNPC[tid] = PC[tid] + (2 * instSize);
  96
  97                     delaySlotInfo[tid].targetReady = false;
  98
  99                     DPRINTF(InOrderFetchSeq, "[tid:%i]: Setting PC to delay "
 100                             "slot target\n",tid);
 101                 }
 102
 103                 inst->setPC(PC[tid]);
 104                 inst->setNextPC(PC[tid] + instSize);
 105                 inst->setNextNPC(PC[tid] + (instSize * 2));
 106
 107 #if ISA_HAS_DELAY_SLOT
 108                 inst->setPredTarg(inst->readNextNPC());
 109 #else
 110                 inst->setPredTarg(inst->readNextPC());
 111 #endif
 112                 inst->setMemAddr(PC[tid]);
 113                 inst->setSeqNum(cpu->getAndIncrementInstSeq(tid));
 114
 115                 DPRINTF(InOrderFetchSeq, "[tid:%i]: Assigning [sn:%i] to "
 116                         "PC %08p, NPC %08p, NNPC %08p\n", tid,
 117                         inst->seqNum, inst->readPC(), inst->readNextPC(),
 118                         inst->readNextNPC());
 119
 120                 if (delaySlotInfo[tid].numInsts > 0) {
 121                     --delaySlotInfo[tid].numInsts;
 122
 123                     // It's OK to set PC to target of branch
 124                     if (delaySlotInfo[tid].numInsts == 0) {
 125                         delaySlotInfo[tid].targetReady = true;
 126                     }
 127
 128                     DPRINTF(InOrderFetchSeq, "[tid:%i]: %i delay slot inst(s) "
 129                             "left to process.\n", tid,
 130                             delaySlotInfo[tid].numInsts);
 131                 }
 132
 133                 PC[tid] = nextPC[tid];
 134                 nextPC[tid] = nextNPC[tid];
 135                 nextNPC[tid] += instSize;
 136
 137                 fs_req->done();
 138             } else {
 139                 DPRINTF(InOrderStall, "STALL: [tid:%i]: NPC not valid\n", tid);
 140                 fs_req->setCompleted(false);
 141             }
 142         }
 143         break;
 144
 145       case UpdateTargetPC:
 146         {
 147             if (inst->isControl()) {
 148                 // If it's a return, then we must wait for resolved address.
 149                 if (inst->isReturn() && !inst->predTaken()) {
 150                     cpu->pipelineStage[stage_num]->toPrevStages->stageBlock[stage_num][tid] = true;
 151                     pcValid[tid] = false;
 152                     pcBlockStage[tid] = stage_num;
 153                 } else if (inst->isCondDelaySlot() && !inst->predTaken()) {
 154                 // Not-Taken AND Conditional Control
 155                     DPRINTF(InOrderFetchSeq, "[tid:%i]: [sn:%i]: [PC:%08p] "
 156                             "Predicted Not-Taken Cond. "
 157                             "Delay inst. Skipping delay slot and  Updating PC to %08p\n",
 158                             tid, inst->seqNum, inst->readPC(), inst->readPredTarg());
 159
 160                     DPRINTF(InOrderFetchSeq, "[tid:%i] Setting up squash to start from stage %i, after [sn:%i].\n",
 161                             tid, stage_num, seq_num);
 162
 163                     inst->bdelaySeqNum = seq_num;
 164                     inst->squashingStage = stage_num;
 165
 166                     squashAfterInst(inst, stage_num, tid);
 167                 } else if (!inst->isCondDelaySlot() && !inst->predTaken()) {
 168                     // Not-Taken Control
 169                     DPRINTF(InOrderFetchSeq, "[tid:%i]: [sn:%i]: Predicted "
 170                             "Not-Taken Control "
 171                             "inst. updating PC to %08p\n", tid, inst->seqNum,
 172                             inst->readNextPC());
 173 #if ISA_HAS_DELAY_SLOT
 174                     ++delaySlotInfo[tid].numInsts;
 175                     delaySlotInfo[tid].targetReady = false;
 176                     delaySlotInfo[tid].targetAddr = inst->readNextNPC();
 177 #else
 178                     assert(delaySlotInfo[tid].numInsts == 0);
 179 #endif
 180                 } else if (inst->predTaken()) {
 181                     // Taken Control
 182 #if ISA_HAS_DELAY_SLOT
 183                     ++delaySlotInfo[tid].numInsts;
 184                     delaySlotInfo[tid].targetReady = false;
 185                     delaySlotInfo[tid].targetAddr = inst->readPredTarg();
 186
 187                     DPRINTF(InOrderFetchSeq, "[tid:%i]: [sn:%i] Updating delay"
 188                             " slot target to PC %08p\n", tid, inst->seqNum,
 189                             inst->readPredTarg());
 190                     inst->bdelaySeqNum = seq_num + 1;
 191 #else
 192                     inst->bdelaySeqNum = seq_num;
 193                     assert(delaySlotInfo[tid].numInsts == 0);
 194 #endif
 195
 196                     inst->squashingStage = stage_num;
 197
 198                     DPRINTF(InOrderFetchSeq, "[tid:%i] Setting up squash to "
 199                             "start from stage %i, after [sn:%i].\n",
 200                             tid, stage_num, inst->bdelaySeqNum);
 201
 202                     // Do Squashing
 203                     squashAfterInst(inst, stage_num, tid);
 204                 }
 205             } else {
 206                 DPRINTF(InOrderFetchSeq, "[tid:%i]: [sn:%i]: Ignoring branch "
 207                         "target update since then is not a control "
 208                         "instruction.\n", tid, inst->seqNum);
 209             }
 210
 211             fs_req->done();
 212         }
 213         break;
 214
 215       default:
 216         fatal("Unrecognized command to %s", resName);
 217     }
 218 }
 219
 220 inline void
 221 FetchSeqUnit::squashAfterInst(DynInstPtr inst, int stage_num, ThreadID tid)
 222 {
 223     // Squash In Pipeline Stage
 224     cpu->pipelineStage[stage_num]->squashDueToBranch(inst, tid);
 225
 226     // Squash inside current resource, so if there needs to be fetching on
 227     // same cycle the fetch information will be correct.
 228     // squash(inst, stage_num, inst->bdelaySeqNum, tid);
 229
 230     // Schedule Squash Through-out Resource Pool
 231     cpu->resPool->scheduleEvent((InOrderCPU::CPUEventType)ResourcePool::SquashAll, inst, 0);
 232 }
 233 void
 234 FetchSeqUnit::squash(DynInstPtr inst, int squash_stage,
 235                      InstSeqNum squash_seq_num, ThreadID tid)
 236 {
 237     DPRINTF(InOrderFetchSeq, "[tid:%i]: Updating due to squash from stage %i."
 238             "\n", tid, squash_stage);
 239
 240     InstSeqNum done_seq_num = inst->bdelaySeqNum;
 241
 242     // Handles the case where we are squashing because of something that is
 243     // not a branch...like a memory stall
 244     Addr new_PC = (inst->isControl()) ?
 245         inst->readPredTarg() : inst->readPC() + instSize;
 246
 247     if (squashSeqNum[tid] <= done_seq_num &&
 248         lastSquashCycle[tid] == curTick) {
 249         DPRINTF(InOrderFetchSeq, "[tid:%i]: Ignoring squash from stage %i, "
 250                 "since there is an outstanding squash that is older.\n",
 251                 tid, squash_stage);
 252     } else {
 253         squashSeqNum[tid] = done_seq_num;
 254         lastSquashCycle[tid] = curTick;
 255
 256         // If The very next instruction number is the done seq. num,
 257         // then we haven't seen the delay slot yet ... if it isn't
 258         // the last done_seq_num then this is the delay slot inst.
 259         if (cpu->nextInstSeqNum(tid) != done_seq_num &&
 260             !inst->procDelaySlotOnMispred) {
 261             delaySlotInfo[tid].numInsts = 0;
 262             delaySlotInfo[tid].targetReady = false;
 263
 264             // Reset PC
 265             PC[tid] = new_PC;
 266             nextPC[tid] = new_PC + instSize;
 267             nextNPC[tid] = new_PC + (2 * instSize);
 268
 269             DPRINTF(InOrderFetchSeq, "[tid:%i]: Setting PC to %08p.\n",
 270                     tid, PC[tid]);
 271         } else {
 272 #if !ISA_HAS_DELAY_SLOT
 273             assert(0);
 274 #endif
 275
 276             delaySlotInfo[tid].numInsts = 1;
 277             delaySlotInfo[tid].targetReady = false;
 278             delaySlotInfo[tid].targetAddr = (inst->procDelaySlotOnMispred) ?
 279                 inst->branchTarget() : new_PC;
 280
 281             // Reset PC to Delay Slot Instruction
 282             if (inst->procDelaySlotOnMispred) {
 283                 PC[tid] = new_PC;
 284                 nextPC[tid] = new_PC + instSize;
 285                 nextNPC[tid] = new_PC + (2 * instSize);
 286             }
 287
 288         }
 289
 290         // Unblock Any Stages Waiting for this information to be updated ...
 291         if (!pcValid[tid]) {
 292             cpu->pipelineStage[pcBlockStage[tid]]->
 293                 toPrevStages->stageUnblock[pcBlockStage[tid]][tid] = true;
 294         }
 295
 296         pcValid[tid] = true;
 297     }
 298
 299     Resource::squash(inst, squash_stage, squash_seq_num, tid);
 300 }
 301
 302 FetchSeqUnit::FetchSeqEvent::FetchSeqEvent()
 303     : ResourceEvent()
 304 { }
 305
 306 void
 307 FetchSeqUnit::FetchSeqEvent::process()
 308 {
 309     FetchSeqUnit* fs_res = dynamic_cast<FetchSeqUnit*>(resource);
 310     assert(fs_res);
 311
 312     for (int i=0; i < MaxThreads; i++) {
 313         fs_res->PC[i] = fs_res->cpu->readPC(i);
 314         fs_res->nextPC[i] = fs_res->cpu->readNextPC(i);
 315         fs_res->nextNPC[i] = fs_res->cpu->readNextNPC(i);
 316         DPRINTF(InOrderFetchSeq, "[tid:%i]: Setting PC:%08p NPC:%08p "
 317                 "NNPC:%08p.\n", fs_res->PC[i], fs_res->nextPC[i],
 318                 fs_res->nextNPC[i]);
 319
 320         fs_res->pcValid[i] = true;
 321     }
 322
 323     //cpu->fetchPriorityList.push_back(tid);
 324 }
 325
 326
 327 void
 328 FetchSeqUnit::activateThread(ThreadID tid)
 329 {
 330     pcValid[tid] = true;
 331
 332     PC[tid] = cpu->readPC(tid);
 333     nextPC[tid] = cpu->readNextPC(tid);
 334     nextNPC[tid] = cpu->readNextNPC(tid);
 335
 336     cpu->fetchPriorityList.push_back(tid);
 337
 338     DPRINTF(InOrderFetchSeq, "[tid:%i]: Reading PC:%08p NPC:%08p "
 339             "NNPC:%08p.\n", tid, PC[tid], nextPC[tid], nextNPC[tid]);
 340 }
 341
 342 void
 343 FetchSeqUnit::deactivateThread(ThreadID tid)
 344 {
 345     delaySlotInfo[tid].numInsts = 0;
 346     delaySlotInfo[tid].targetReady = false;
 347
 348     pcValid[tid] = false;
 349     pcBlockStage[tid] = 0;
 350
 351     squashSeqNum[tid] = (InstSeqNum)-1;
 352     lastSquashCycle[tid] = 0;
 353
 354     list<ThreadID>::iterator thread_it = find(cpu->fetchPriorityList.begin(),
 355                                               cpu->fetchPriorityList.end(),
 356                                               tid);
 357
 358     if (thread_it != cpu->fetchPriorityList.end())
 359         cpu->fetchPriorityList.erase(thread_it);
 360 }
 361
 362 void
 363 FetchSeqUnit::suspendThread(ThreadID tid)
 364 {
 365     deactivateThread(tid);
 366 }
 367
 368 void
 369 FetchSeqUnit::updateAfterContextSwitch(DynInstPtr inst, ThreadID tid)
 370 {
 371     pcValid[tid] = true;
 372
 373     if (cpu->thread[tid]->lastGradIsBranch) {
 374         /** This function assumes that the instruction causing the context
 375          *  switch was right after the branch. Thus, if it's not, then
 376          *  we are updating incorrectly here
 377          */
 378         assert(cpu->thread[tid]->lastBranchNextPC == inst->readPC());
 379
 380         PC[tid] = cpu->thread[tid]->lastBranchNextNPC;
 381         nextPC[tid] = PC[tid] + instSize;
 382         nextNPC[tid] = nextPC[tid] + instSize;
 383     } else {
 384         PC[tid] = inst->readNextPC();
 385         nextPC[tid] = inst->readNextNPC();
 386         nextNPC[tid] = inst->readNextNPC() + instSize;
 387     }
 388
 389     DPRINTF(InOrderFetchSeq, "[tid:%i]: Updating PCs due to Context Switch."
 390             "Assigning  PC:%08p NPC:%08p NNPC:%08p.\n", tid, PC[tid],
 391             nextPC[tid], nextNPC[tid]);
 392 }