src/cpu/inorder/resources/fetch_seq_unit.hh

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #ifndef __CPU_INORDER_FETCH_SEQ_UNIT_HH__
  33 #define __CPU_INORDER_FETCH_SEQ_UNIT_HH__
  34
  35 #include <list>
  36 #include <string>
  37 #include <vector>
  38
  39 #include "config/the_isa.hh"
  40 #include "cpu/inorder/cpu.hh"
  41 #include "cpu/inorder/inorder_dyn_inst.hh"
  42 #include "cpu/inorder/pipeline_traits.hh"
  43 #include "cpu/inorder/resource.hh"
  44
  45 class FetchSeqUnit : public Resource {
  46   public:
  47     typedef ThePipeline::DynInstPtr DynInstPtr;
  48     typedef std::list<DynInstPtr>::iterator ListIt;
  49
  50     enum Command {
  51         AssignNextPC,
  52         UpdateTargetPC
  53     };
  54
  55   public:
  56     FetchSeqUnit(std::string res_name, int res_id, int res_width,
  57               int res_latency, InOrderCPU *_cpu, ThePipeline::Params *params);
  58     ~FetchSeqUnit();
  59
  60     void init();
  61     void activateThread(ThreadID tid);
  62     void deactivateThread(ThreadID tid);
  63     void suspendThread(ThreadID tid);
  64     void execute(int slot_num);
  65     void updateAfterContextSwitch(DynInstPtr inst, ThreadID tid);
  66
  67
  68     /** Update to correct PC from a squash */
  69     void squash(DynInstPtr inst, int squash_stage,
  70                 InstSeqNum squash_seq_num, ThreadID tid);
  71
  72     /** Update to correct PC from a trap */
  73     void trap(Fault fault, ThreadID tid, DynInstPtr inst);
  74
  75   protected:
  76     unsigned instSize;
  77
  78     bool pcValid[ThePipeline::MaxThreads];
  79     int pcBlockStage[ThePipeline::MaxThreads];
  80
  81     TheISA::PCState pc[ThePipeline::MaxThreads];
  82
  83     /** Squash Seq. Nums*/
  84     InstSeqNum squashSeqNum[ThePipeline::MaxThreads];
  85
  86     /** Squash Seq. Nums*/
  87     Tick lastSquashCycle[ThePipeline::MaxThreads];
  88
  89     /** @todo: Add Resource Stats Here */
  90
  91   public:
  92     class FetchSeqEvent : public ResourceEvent {
  93       public:
  94         /** Constructs a resource event. */
  95         FetchSeqEvent();
  96         ~FetchSeqEvent() {}
  97
  98         /** Processes a resource event. */
  99         void process();
 100     };
 101
 102 };
 103
 104 #endif