src/cpu/inorder/resources/fetch_seq_unit.hh

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #ifndef __CPU_INORDER_FETCH_SEQ_UNIT_HH__
  33 #define __CPU_INORDER_FETCH_SEQ_UNIT_HH__
  34
  35 #include <vector>
  36 #include <list>
  37 #include <string>
  38
  39 #include "cpu/inorder/resource.hh"
  40 #include "cpu/inorder/inorder_dyn_inst.hh"
  41 #include "cpu/inorder/pipeline_traits.hh"
  42 #include "cpu/inorder/cpu.hh"
  43
  44 class FetchSeqUnit : public Resource {
  45   public:
  46     typedef ThePipeline::DynInstPtr DynInstPtr;
  47
  48     enum Command {
  49         AssignNextPC,
  50         UpdateTargetPC
  51     };
  52
  53   public:
  54     FetchSeqUnit(std::string res_name, int res_id, int res_width,
  55               int res_latency, InOrderCPU *_cpu, ThePipeline::Params *params);
  56     virtual ~FetchSeqUnit() {}
  57
  58     virtual void init();
  59     virtual void activateThread(ThreadID tid);
  60     virtual void deactivateThread(ThreadID tid);
  61     virtual void execute(int slot_num);
  62
  63     /** Override default Resource squash sequence. This actually,
  64      *  looks in the global communication buffer to get squash
  65      *  info
  66      */
  67     virtual void squash(DynInstPtr inst, int squash_stage,
  68                         InstSeqNum squash_seq_num, ThreadID tid);
  69
  70
  71     inline void squashAfterInst(DynInstPtr inst, int stage_num, ThreadID tid);
  72
  73   protected:
  74     unsigned instSize;
  75
  76     bool pcValid[ThePipeline::MaxThreads];
  77     int pcBlockStage[ThePipeline::MaxThreads];
  78
  79     TheISA::IntReg PC[ThePipeline::MaxThreads];
  80     TheISA::IntReg nextPC[ThePipeline::MaxThreads];
  81     TheISA::IntReg nextNPC[ThePipeline::MaxThreads];
  82
  83     /** Tracks delay slot information for threads in ISAs which use
  84      *  delay slots;
  85      */
  86     struct DelaySlotInfo {
  87         InstSeqNum delaySlotSeqNum;
  88         InstSeqNum branchSeqNum;
  89         int numInsts;
  90         Addr targetAddr;
  91         bool targetReady;
  92     };
  93
  94     DelaySlotInfo delaySlotInfo[ThePipeline::MaxThreads];
  95
  96     /** Squash Seq. Nums*/
  97     InstSeqNum squashSeqNum[ThePipeline::MaxThreads];
  98
  99     /** Squash Seq. Nums*/
 100     Tick lastSquashCycle[ThePipeline::MaxThreads];
 101
 102     /** @todo: Add Resource Stats Here */
 103
 104   public:
 105     class FetchSeqEvent : public ResourceEvent {
 106       public:
 107         /** Constructs a resource event. */
 108         FetchSeqEvent();
 109         virtual ~FetchSeqEvent() {}
 110
 111         /** Processes a resource event. */
 112         virtual void process();
 113     };
 114
 115 };
 116
 117 #endif