src/cpu/inorder/resources/fetch_seq_unit.hh

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #ifndef __CPU_INORDER_FETCH_SEQ_UNIT_HH__
  33 #define __CPU_INORDER_FETCH_SEQ_UNIT_HH__
  34
  35 #include <vector>
  36 #include <list>
  37 #include <string>
  38
  39 #include "config/the_isa.hh"
  40 #include "cpu/inorder/resource.hh"
  41 #include "cpu/inorder/inorder_dyn_inst.hh"
  42 #include "cpu/inorder/pipeline_traits.hh"
  43 #include "cpu/inorder/cpu.hh"
  44
  45 class FetchSeqUnit : public Resource {
  46   public:
  47     typedef ThePipeline::DynInstPtr DynInstPtr;
  48
  49     enum Command {
  50         AssignNextPC,
  51         UpdateTargetPC
  52     };
  53
  54   public:
  55     FetchSeqUnit(std::string res_name, int res_id, int res_width,
  56               int res_latency, InOrderCPU *_cpu, ThePipeline::Params *params);
  57     virtual ~FetchSeqUnit() {}
  58
  59     virtual void init();
  60     virtual void activateThread(ThreadID tid);
  61     virtual void deactivateThread(ThreadID tid);
  62     virtual void suspendThread(ThreadID tid);
  63     virtual void execute(int slot_num);
  64
  65     /** Override default Resource squash sequence. This actually,
  66      *  looks in the global communication buffer to get squash
  67      *  info
  68      */
  69     virtual void squash(DynInstPtr inst, int squash_stage,
  70                         InstSeqNum squash_seq_num, ThreadID tid);
  71
  72
  73     inline void squashAfterInst(DynInstPtr inst, int stage_num, ThreadID tid);
  74
  75   protected:
  76     unsigned instSize;
  77
  78     bool pcValid[ThePipeline::MaxThreads];
  79     int pcBlockStage[ThePipeline::MaxThreads];
  80
  81     TheISA::IntReg PC[ThePipeline::MaxThreads];
  82     TheISA::IntReg nextPC[ThePipeline::MaxThreads];
  83     TheISA::IntReg nextNPC[ThePipeline::MaxThreads];
  84
  85     /** Tracks delay slot information for threads in ISAs which use
  86      *  delay slots;
  87      */
  88     struct DelaySlotInfo {
  89         InstSeqNum delaySlotSeqNum;
  90         InstSeqNum branchSeqNum;
  91         int numInsts;
  92         Addr targetAddr;
  93         bool targetReady;
  94     };
  95
  96     DelaySlotInfo delaySlotInfo[ThePipeline::MaxThreads];
  97
  98     /** Squash Seq. Nums*/
  99     InstSeqNum squashSeqNum[ThePipeline::MaxThreads];
 100
 101     /** Squash Seq. Nums*/
 102     Tick lastSquashCycle[ThePipeline::MaxThreads];
 103
 104     /** @todo: Add Resource Stats Here */
 105
 106   public:
 107     class FetchSeqEvent : public ResourceEvent {
 108       public:
 109         /** Constructs a resource event. */
 110         FetchSeqEvent();
 111         virtual ~FetchSeqEvent() {}
 112
 113         /** Processes a resource event. */
 114         virtual void process();
 115     };
 116
 117 };
 118
 119 #endif