src/cpu/inorder/resources/fetch_unit.cc

   1 /*
   2  * Copyright (c) 2011 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #include <list>
  33 #include <vector>
  34
  35 #include "arch/isa_traits.hh"
  36 #include "arch/locked_mem.hh"
  37 #include "arch/predecoder.hh"
  38 #include "arch/utility.hh"
  39 #include "config/the_isa.hh"
  40 #include "cpu/inorder/resources/cache_unit.hh"
  41 #include "cpu/inorder/resources/fetch_unit.hh"
  42 #include "cpu/inorder/cpu.hh"
  43 #include "cpu/inorder/pipeline_traits.hh"
  44 #include "cpu/inorder/resource_pool.hh"
  45 #include "debug/Activity.hh"
  46 #include "debug/InOrderCachePort.hh"
  47 #include "debug/InOrderStall.hh"
  48 #include "debug/RefCount.hh"
  49 #include "debug/ThreadModel.hh"
  50 #include "mem/request.hh"
  51
  52 using namespace std;
  53 using namespace TheISA;
  54 using namespace ThePipeline;
  55
  56 FetchUnit::FetchUnit(string res_name, int res_id, int res_width,
  57                      int res_latency, InOrderCPU *_cpu,
  58                      ThePipeline::Params *params)
  59     : CacheUnit(res_name, res_id, res_width, res_latency, _cpu, params),
  60       instSize(sizeof(TheISA::MachInst)), fetchBuffSize(params->fetchBuffSize),
  61       predecoder(NULL)
  62 { }
  63
  64 FetchUnit::~FetchUnit()
  65 {
  66     std::list<FetchBlock*>::iterator fetch_it = fetchBuffer.begin();
  67     std::list<FetchBlock*>::iterator end_it = fetchBuffer.end();
  68     while (fetch_it != end_it) {
  69         delete (*fetch_it)->block;
  70         delete *fetch_it;
  71         fetch_it++;
  72     }
  73     fetchBuffer.clear();
  74
  75
  76     std::list<FetchBlock*>::iterator pend_it = pendingFetch.begin();
  77     std::list<FetchBlock*>::iterator pend_end = pendingFetch.end();
  78     while (pend_it != pend_end) {
  79         if ((*pend_it)->block) {
  80             delete (*pend_it)->block;
  81         }
  82
  83         delete *pend_it;
  84         pend_it++;
  85     }
  86     pendingFetch.clear();
  87 }
  88
  89 void
  90 FetchUnit::createMachInst(std::list<FetchBlock*>::iterator fetch_it,
  91                           DynInstPtr inst)
  92 {
  93     ExtMachInst ext_inst;
  94     Addr block_addr = cacheBlockAlign(inst->getMemAddr());
  95     Addr fetch_addr = inst->getMemAddr();
  96     unsigned fetch_offset = (fetch_addr - block_addr) / instSize;
  97     ThreadID tid = inst->readTid();
  98     TheISA::PCState instPC = inst->pcState();
  99
 100
 101     DPRINTF(InOrderCachePort, "Creating instruction [sn:%i] w/fetch data @"
 102             "addr:%08p block:%08p\n", inst->seqNum, fetch_addr, block_addr);
 103
 104     assert((*fetch_it)->valid);
 105
 106     TheISA::MachInst *fetchInsts =
 107         reinterpret_cast<TheISA::MachInst *>((*fetch_it)->block);
 108
 109     MachInst mach_inst =
 110         TheISA::gtoh(fetchInsts[fetch_offset]);
 111
 112     predecoder.setTC(cpu->thread[tid]->getTC());
 113     predecoder.moreBytes(instPC, inst->instAddr(), mach_inst);
 114     assert(predecoder.extMachInstReady());
 115     ext_inst = predecoder.getExtMachInst(instPC);
 116
 117     inst->pcState(instPC);
 118     inst->setMachInst(ext_inst);
 119 }
 120
 121 int
 122 FetchUnit::getSlot(DynInstPtr inst)
 123 {
 124     if (tlbBlocked[inst->threadNumber]) {
 125         return -1;
 126     }
 127
 128     if (!inst->validMemAddr()) {
 129         panic("[tid:%i][sn:%i] Mem. Addr. must be set before requesting "
 130               "cache access\n", inst->readTid(), inst->seqNum);
 131     }
 132
 133     int new_slot = Resource::getSlot(inst);
 134
 135     if (new_slot == -1)
 136         return -1;
 137
 138     inst->memTime = curTick();
 139     return new_slot;
 140 }
 141
 142 void
 143 FetchUnit::removeAddrDependency(DynInstPtr inst)
 144 {
 145     inst->unsetMemAddr();
 146 }
 147
 148 ResReqPtr
 149 FetchUnit::getRequest(DynInstPtr inst, int stage_num, int res_idx,
 150                      int slot_num, unsigned cmd)
 151 {
 152     ScheduleEntry* sched_entry = *inst->curSkedEntry;
 153     CacheRequest* cache_req = dynamic_cast<CacheRequest*>(reqs[slot_num]);
 154
 155     if (!inst->validMemAddr()) {
 156         panic("Mem. Addr. must be set before requesting cache access\n");
 157     }
 158
 159     assert(sched_entry->cmd == InitiateFetch);
 160
 161     DPRINTF(InOrderCachePort,
 162             "[tid:%i]: Fetch request from [sn:%i] for addr %08p\n",
 163             inst->readTid(), inst->seqNum, inst->getMemAddr());
 164
 165     cache_req->setRequest(inst, stage_num, id, slot_num,
 166                           sched_entry->cmd, MemCmd::ReadReq,
 167                           inst->curSkedEntry->idx);
 168
 169     return cache_req;
 170 }
 171
 172 void
 173 FetchUnit::setupMemRequest(DynInstPtr inst, CacheReqPtr cache_req,
 174                            int acc_size, int flags)
 175 {
 176     ThreadID tid = inst->readTid();
 177     Addr aligned_addr = cacheBlockAlign(inst->getMemAddr());
 178     cache_req->memReq =
 179             new Request(tid, aligned_addr, acc_size, flags,
 180                         inst->instAddr(), cpu->readCpuId(), tid);
 181 }
 182
 183 std::list<FetchUnit::FetchBlock*>::iterator
 184 FetchUnit::findBlock(std::list<FetchBlock*> &fetch_blocks, int asid,
 185                      Addr block_addr)
 186 {
 187     std::list<FetchBlock*>::iterator fetch_it = fetch_blocks.begin();
 188     std::list<FetchBlock*>::iterator end_it = fetch_blocks.end();
 189
 190     while (fetch_it != end_it) {
 191         if ((*fetch_it)->asid == asid &&
 192             (*fetch_it)->addr == block_addr) {
 193             return fetch_it;
 194         }
 195
 196         fetch_it++;
 197     }
 198
 199     return fetch_it;
 200 }
 201
 202 std::list<FetchUnit::FetchBlock*>::iterator
 203 FetchUnit::findReplacementBlock()
 204 {
 205     std::list<FetchBlock*>::iterator fetch_it = fetchBuffer.begin();
 206     std::list<FetchBlock*>::iterator end_it = fetchBuffer.end();
 207
 208     while (fetch_it != end_it) {
 209         if ((*fetch_it)->cnt == 0) {
 210             return fetch_it;
 211         } else {
 212             DPRINTF(InOrderCachePort, "Block %08p has %i insts pending.\n",
 213                     (*fetch_it)->addr, (*fetch_it)->cnt);
 214         }
 215         fetch_it++;
 216     }
 217
 218     return fetch_it;
 219 }
 220
 221 void
 222 FetchUnit::markBlockUsed(std::list<FetchBlock*>::iterator block_it)
 223 {
 224     // Move block from whatever location it is in fetch buffer
 225     // to the back (represents most-recently-used location)
 226     if (block_it != fetchBuffer.end()) {
 227         FetchBlock *mru_blk = *block_it;
 228         fetchBuffer.erase(block_it);
 229         fetchBuffer.push_back(mru_blk);
 230     }
 231 }
 232
 233 void
 234 FetchUnit::execute(int slot_num)
 235 {
 236     CacheReqPtr cache_req = dynamic_cast<CacheReqPtr>(reqs[slot_num]);
 237     assert(cache_req);
 238
 239     if (cachePortBlocked && cache_req->cmd == InitiateFetch) {
 240         DPRINTF(InOrderCachePort, "Cache Port Blocked. Cannot Access\n");
 241         cache_req->done(false);
 242         return;
 243     }
 244
 245     DynInstPtr inst = cache_req->inst;
 246     ThreadID tid = inst->readTid();
 247     Addr block_addr = cacheBlockAlign(inst->getMemAddr());
 248     int asid = cpu->asid[tid];
 249
 250     inst->fault = NoFault;
 251
 252     switch (cache_req->cmd)
 253     {
 254       case InitiateFetch:
 255         {
 256             // Check to see if we've already got this request buffered
 257             // or pending to be buffered
 258             bool do_fetch = true;
 259             std::list<FetchBlock*>::iterator pending_it;
 260             pending_it = findBlock(pendingFetch, asid, block_addr);
 261             if (pending_it != pendingFetch.end()) {
 262                 (*pending_it)->cnt++;
 263                 do_fetch = false;
 264
 265                 DPRINTF(InOrderCachePort, "%08p is a pending fetch block "
 266                         "(pending:%i).\n", block_addr,
 267                         (*pending_it)->cnt);
 268             } else if (pendingFetch.size() < fetchBuffSize) {
 269                 std::list<FetchBlock*>::iterator buff_it;
 270                 buff_it = findBlock(fetchBuffer, asid, block_addr);
 271                 if (buff_it  != fetchBuffer.end()) {
 272                     (*buff_it)->cnt++;
 273                     do_fetch = false;
 274
 275                     DPRINTF(InOrderCachePort, "%08p is in fetch buffer"
 276                             "(pending:%i).\n", block_addr, (*buff_it)->cnt);
 277                 }
 278             }
 279
 280             if (!do_fetch) {
 281                 DPRINTF(InOrderCachePort, "Inst. [sn:%i] marked to be filled "
 282                         "through fetch buffer.\n", inst->seqNum);
 283                 cache_req->fetchBufferFill = true;
 284                 cache_req->setCompleted(true);
 285                 return;
 286             }
 287
 288             // Check to see if there is room in the fetchbuffer for this instruction.
 289             // If not, block this request.
 290             if (pendingFetch.size() >= fetchBuffSize) {
 291                 DPRINTF(InOrderCachePort, "No room available in fetch buffer.\n");
 292                 cache_req->done();
 293                 return;
 294             }
 295
 296             doTLBAccess(inst, cache_req, cacheBlkSize, 0, TheISA::TLB::Execute);
 297
 298             if (inst->fault == NoFault) {
 299                 DPRINTF(InOrderCachePort,
 300                         "[tid:%u]: Initiating fetch access to %s for "
 301                         "addr:%#x (block:%#x)\n", tid, name(),
 302                         cache_req->inst->getMemAddr(), block_addr);
 303
 304                 cache_req->reqData = new uint8_t[cacheBlkSize];
 305
 306                 inst->setCurResSlot(slot_num);
 307
 308                 doCacheAccess(inst);
 309
 310                 if (cache_req->isMemAccPending()) {
 311                     pendingFetch.push_back(new FetchBlock(asid, block_addr));
 312                 }
 313             }
 314
 315             break;
 316         }
 317
 318       case CompleteFetch:
 319         if (cache_req->fetchBufferFill) {
 320             // Block request if it's depending on a previous fetch, but it hasnt made it yet
 321             std::list<FetchBlock*>::iterator fetch_it = findBlock(fetchBuffer, asid, block_addr);
 322             if (fetch_it == fetchBuffer.end()) {
 323                 DPRINTF(InOrderCachePort, "%#x not available yet\n",
 324                         block_addr);
 325                 cache_req->setCompleted(false);
 326                 return;
 327             }
 328
 329             // Make New Instruction
 330             createMachInst(fetch_it, inst);
 331             if (inst->traceData) {
 332                 inst->traceData->setStaticInst(inst->staticInst);
 333                 inst->traceData->setPC(inst->pcState());
 334             }
 335
 336             // FetchBuffer Book-Keeping
 337             (*fetch_it)->cnt--;
 338             assert((*fetch_it)->cnt >= 0);
 339             markBlockUsed(fetch_it);
 340
 341             cache_req->done();
 342             return;
 343         }
 344
 345         if (cache_req->isMemAccComplete()) {
 346             if (fetchBuffer.size() >= fetchBuffSize) {
 347                 // If there is no replacement block, then we'll just have
 348                 // to wait till that gets cleared before satisfying the fetch
 349                 // for this instruction
 350                 std::list<FetchBlock*>::iterator repl_it  =
 351                     findReplacementBlock();
 352                 if (repl_it == fetchBuffer.end()) {
 353                     DPRINTF(InOrderCachePort, "Unable to find replacement block"
 354                             " and complete fetch.\n");
 355                     cache_req->setCompleted(false);
 356                     return;
 357                 }
 358
 359                 delete [] (*repl_it)->block;
 360                 delete *repl_it;
 361                 fetchBuffer.erase(repl_it);
 362             }
 363
 364             DPRINTF(InOrderCachePort,
 365                     "[tid:%i]: Completing Fetch Access for [sn:%i]\n",
 366                     tid, inst->seqNum);
 367
 368             // Make New Instruction
 369             std::list<FetchBlock*>::iterator fetch_it  =
 370                 findBlock(pendingFetch, asid, block_addr);
 371
 372             assert(fetch_it != pendingFetch.end());
 373             assert((*fetch_it)->valid);
 374
 375             createMachInst(fetch_it, inst);
 376             if (inst->traceData) {
 377                 inst->traceData->setStaticInst(inst->staticInst);
 378                 inst->traceData->setPC(inst->pcState());
 379             }
 380
 381
 382             // Update instructions waiting on new fetch block
 383             FetchBlock *new_block = (*fetch_it);
 384             new_block->cnt--;
 385             assert(new_block->cnt >= 0);
 386
 387             // Finally, update FetchBuffer w/Pending Block into the
 388             // MRU location
 389             pendingFetch.erase(fetch_it);
 390             fetchBuffer.push_back(new_block);
 391
 392             DPRINTF(InOrderCachePort, "[tid:%i]: Instruction [sn:%i] is: %s\n",
 393                     tid, inst->seqNum,
 394                     inst->staticInst->disassemble(inst->instAddr()));
 395
 396             inst->unsetMemAddr();
 397
 398             cache_req->done();
 399         } else {
 400             DPRINTF(InOrderCachePort,
 401                      "[tid:%i]: [sn:%i]: Unable to Complete Fetch Access\n",
 402                     tid, inst->seqNum);
 403             DPRINTF(InOrderStall,
 404                     "STALL: [tid:%i]: Fetch miss from %08p\n",
 405                     tid, cache_req->inst->instAddr());
 406             cache_req->setCompleted(false);
 407             // NOTE: For SwitchOnCacheMiss ThreadModel, we *don't* switch on
 408             //       fetch miss, but we could ...
 409             // cache_req->setMemStall(true);
 410         }
 411         break;
 412
 413       default:
 414         fatal("Unrecognized command to %s", resName);
 415     }
 416 }
 417
 418 void
 419 FetchUnit::processCacheCompletion(PacketPtr pkt)
 420 {
 421     // Cast to correct packet type
 422     CacheReqPacket* cache_pkt = dynamic_cast<CacheReqPacket*>(pkt);
 423     assert(cache_pkt);
 424
 425     DPRINTF(InOrderCachePort, "Finished request for %x\n",
 426             cache_pkt->getAddr());
 427
 428     if (processSquash(cache_pkt))
 429         return;
 430
 431     Addr block_addr = cacheBlockAlign(cache_pkt->cacheReq->
 432                                       getInst()->getMemAddr());
 433
 434     DPRINTF(InOrderCachePort,
 435             "[tid:%u]: [sn:%i]: Waking from fetch access to addr:%#x(phys:%#x), size:%i\n",
 436             cache_pkt->cacheReq->getInst()->readTid(),
 437             cache_pkt->cacheReq->getInst()->seqNum,
 438             block_addr, cache_pkt->getAddr(), cache_pkt->getSize());
 439
 440     // Cast to correct request type
 441     CacheRequest *cache_req = dynamic_cast<CacheReqPtr>(
 442         findRequest(cache_pkt->cacheReq->getInst(), cache_pkt->instIdx));
 443
 444     if (!cache_req) {
 445         panic("[tid:%u]: [sn:%i]: Can't find slot for fetch access to "
 446               "addr. %08p\n", cache_pkt->cacheReq->getInst()->readTid(),
 447               cache_pkt->cacheReq->getInst()->seqNum,
 448               block_addr);
 449     }
 450
 451     // Get resource request info
 452     unsigned stage_num = cache_req->getStageNum();
 453     DynInstPtr inst = cache_req->inst;
 454     ThreadID tid = cache_req->inst->readTid();
 455     short asid = cpu->asid[tid];
 456
 457     assert(!cache_req->isSquashed());
 458     assert(inst->curSkedEntry->cmd == CompleteFetch);
 459
 460     DPRINTF(InOrderCachePort,
 461             "[tid:%u]: [sn:%i]: Processing fetch access for block %#x\n",
 462             tid, inst->seqNum, block_addr);
 463
 464     std::list<FetchBlock*>::iterator pend_it = findBlock(pendingFetch, asid,
 465                                                          block_addr);
 466     assert(pend_it != pendingFetch.end());
 467
 468     // Copy Data to pendingFetch queue...
 469     (*pend_it)->block = new uint8_t[cacheBlkSize];
 470     memcpy((*pend_it)->block, cache_pkt->getPtr<uint8_t>(), cacheBlkSize);
 471     (*pend_it)->valid = true;
 472
 473     cache_req->setMemAccPending(false);
 474     cache_req->setMemAccCompleted();
 475
 476     if (cache_req->isMemStall() &&
 477         cpu->threadModel == InOrderCPU::SwitchOnCacheMiss) {
 478         DPRINTF(InOrderCachePort, "[tid:%u] Waking up from Cache Miss.\n",
 479                 tid);
 480
 481         cpu->activateContext(tid);
 482
 483         DPRINTF(ThreadModel, "Activating [tid:%i] after return from cache"
 484                 "miss.\n", tid);
 485     }
 486
 487     // Wake up the CPU (if it went to sleep and was waiting on this
 488     // completion event).
 489     cpu->wakeCPU();
 490
 491     DPRINTF(Activity, "[tid:%u] Activating %s due to cache completion\n",
 492             tid, cpu->pipelineStage[stage_num]->name());
 493
 494     cpu->switchToActive(stage_num);
 495 }
 496
 497 void
 498 FetchUnit::squashCacheRequest(CacheReqPtr req_ptr)
 499 {
 500     DynInstPtr inst = req_ptr->getInst();
 501     ThreadID tid = inst->readTid();
 502     Addr block_addr = cacheBlockAlign(inst->getMemAddr());
 503     int asid = cpu->asid[tid];
 504
 505     // Check Fetch Buffer (or pending fetch) for this block and
 506     // update pending counts
 507     std::list<FetchBlock*>::iterator buff_it = findBlock(fetchBuffer,
 508                                                          asid,
 509                                                          block_addr);
 510     if (buff_it != fetchBuffer.end()) {
 511         (*buff_it)->cnt--;
 512         DPRINTF(InOrderCachePort, "[sn:%i] Removing Pending Fetch "
 513                 "for Buffer block %08p (cnt=%i)\n", inst->seqNum,
 514                 block_addr, (*buff_it)->cnt);
 515     } else {
 516         std::list<FetchBlock*>::iterator block_it = findBlock(pendingFetch,
 517                                                               asid,
 518                                                               block_addr);
 519         if (block_it != pendingFetch.end()) {
 520             (*block_it)->cnt--;
 521             if ((*block_it)->cnt == 0) {
 522                 DPRINTF(InOrderCachePort, "[sn:%i] Removing Pending Fetch "
 523                         "for block %08p (cnt=%i)\n", inst->seqNum,
 524                         block_addr, (*block_it)->cnt);
 525                 if ((*block_it)->block) {
 526                     delete [] (*block_it)->block;
 527                 }
 528                 delete *block_it;
 529                 pendingFetch.erase(block_it);
 530             }
 531         }
 532     }
 533
 534     CacheUnit::squashCacheRequest(req_ptr);
 535 }
 536
 537 void
 538 FetchUnit::trap(Fault fault, ThreadID tid, DynInstPtr inst)
 539 {
 540     //@todo: per thread?
 541     predecoder.reset();
 542 }