src/cpu/inorder/resources/fetch_unit.cc

   1 /*
   2  * Copyright (c) 2011 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #include <vector>
  33 #include <list>
  34
  35 #include "arch/isa_traits.hh"
  36 #include "arch/locked_mem.hh"
  37 #include "arch/utility.hh"
  38 #include "arch/predecoder.hh"
  39 #include "config/the_isa.hh"
  40 #include "cpu/inorder/resources/cache_unit.hh"
  41 #include "cpu/inorder/resources/fetch_unit.hh"
  42 #include "cpu/inorder/pipeline_traits.hh"
  43 #include "cpu/inorder/cpu.hh"
  44 #include "cpu/inorder/resource_pool.hh"
  45 #include "mem/request.hh"
  46
  47 using namespace std;
  48 using namespace TheISA;
  49 using namespace ThePipeline;
  50
  51 FetchUnit::FetchUnit(string res_name, int res_id, int res_width,
  52                      int res_latency, InOrderCPU *_cpu,
  53                      ThePipeline::Params *params)
  54     : CacheUnit(res_name, res_id, res_width, res_latency, _cpu, params),
  55       instSize(sizeof(TheISA::MachInst)), fetchBuffSize(params->fetchBuffSize),
  56       predecoder(NULL)
  57 { }
  58
  59 FetchUnit::~FetchUnit()
  60 {
  61     std::list<FetchBlock*>::iterator fetch_it = fetchBuffer.begin();
  62     std::list<FetchBlock*>::iterator end_it = fetchBuffer.end();
  63     while (fetch_it != end_it) {
  64         delete (*fetch_it)->block;
  65         delete *fetch_it;
  66         fetch_it++;
  67     }
  68     fetchBuffer.clear();
  69
  70
  71     std::list<FetchBlock*>::iterator pend_it = pendingFetch.begin();
  72     std::list<FetchBlock*>::iterator pend_end = pendingFetch.end();
  73     while (pend_it != pend_end) {
  74         if ((*pend_it)->block) {
  75             delete (*pend_it)->block;
  76         }
  77
  78         delete *pend_it;
  79         pend_it++;
  80     }
  81     pendingFetch.clear();
  82 }
  83
  84 void
  85 FetchUnit::createMachInst(std::list<FetchBlock*>::iterator fetch_it,
  86                           DynInstPtr inst)
  87 {
  88     ExtMachInst ext_inst;
  89     Addr block_addr = cacheBlockAlign(inst->getMemAddr());
  90     Addr fetch_addr = inst->getMemAddr();
  91     unsigned fetch_offset = (fetch_addr - block_addr) / instSize;
  92     ThreadID tid = inst->readTid();
  93     TheISA::PCState instPC = inst->pcState();
  94
  95
  96     DPRINTF(InOrderCachePort, "Creating instruction [sn:%i] w/fetch data @"
  97             "addr:%08p block:%08p\n", inst->seqNum, fetch_addr, block_addr);
  98
  99     assert((*fetch_it)->valid);
 100
 101     TheISA::MachInst *fetchInsts =
 102         reinterpret_cast<TheISA::MachInst *>((*fetch_it)->block);
 103
 104     MachInst mach_inst =
 105         TheISA::gtoh(fetchInsts[fetch_offset]);
 106
 107     predecoder.setTC(cpu->thread[tid]->getTC());
 108     predecoder.moreBytes(instPC, inst->instAddr(), mach_inst);
 109     ext_inst = predecoder.getExtMachInst(instPC);
 110
 111     inst->pcState(instPC);
 112     inst->setMachInst(ext_inst);
 113 }
 114
 115 int
 116 FetchUnit::getSlot(DynInstPtr inst)
 117 {
 118     if (tlbBlocked[inst->threadNumber]) {
 119         return -1;
 120     }
 121
 122     if (!inst->validMemAddr()) {
 123         panic("[tid:%i][sn:%i] Mem. Addr. must be set before requesting "
 124               "cache access\n", inst->readTid(), inst->seqNum);
 125     }
 126
 127     int new_slot = Resource::getSlot(inst);
 128
 129     if (new_slot == -1)
 130         return -1;
 131
 132     inst->memTime = curTick();
 133     return new_slot;
 134 }
 135
 136 void
 137 FetchUnit::removeAddrDependency(DynInstPtr inst)
 138 {
 139     inst->unsetMemAddr();
 140 }
 141
 142 ResReqPtr
 143 FetchUnit::getRequest(DynInstPtr inst, int stage_num, int res_idx,
 144                      int slot_num, unsigned cmd)
 145 {
 146     ScheduleEntry* sched_entry = *inst->curSkedEntry;
 147     CacheRequest* cache_req = dynamic_cast<CacheRequest*>(reqs[slot_num]);
 148
 149     if (!inst->validMemAddr()) {
 150         panic("Mem. Addr. must be set before requesting cache access\n");
 151     }
 152
 153     assert(sched_entry->cmd == InitiateFetch);
 154
 155     DPRINTF(InOrderCachePort,
 156             "[tid:%i]: Fetch request from [sn:%i] for addr %08p\n",
 157             inst->readTid(), inst->seqNum, inst->getMemAddr());
 158
 159     cache_req->setRequest(inst, stage_num, id, slot_num,
 160                           sched_entry->cmd, MemCmd::ReadReq,
 161                           inst->curSkedEntry->idx);
 162
 163     return cache_req;
 164 }
 165
 166 void
 167 FetchUnit::setupMemRequest(DynInstPtr inst, CacheReqPtr cache_req,
 168                            int acc_size, int flags)
 169 {
 170     ThreadID tid = inst->readTid();
 171     Addr aligned_addr = cacheBlockAlign(inst->getMemAddr());
 172
 173     inst->fetchMemReq =
 174             new Request(tid, aligned_addr, acc_size, flags,
 175                         inst->instAddr(), cpu->readCpuId(), tid);
 176
 177     cache_req->memReq = inst->fetchMemReq;
 178 }
 179
 180 std::list<FetchUnit::FetchBlock*>::iterator
 181 FetchUnit::findBlock(std::list<FetchBlock*> &fetch_blocks, int asid,
 182                      Addr block_addr)
 183 {
 184     std::list<FetchBlock*>::iterator fetch_it = fetch_blocks.begin();
 185     std::list<FetchBlock*>::iterator end_it = fetch_blocks.end();
 186
 187     while (fetch_it != end_it) {
 188         if ((*fetch_it)->asid == asid &&
 189             (*fetch_it)->addr == block_addr) {
 190             return fetch_it;
 191         }
 192
 193         fetch_it++;
 194     }
 195
 196     return fetch_it;
 197 }
 198
 199 std::list<FetchUnit::FetchBlock*>::iterator
 200 FetchUnit::findReplacementBlock()
 201 {
 202     std::list<FetchBlock*>::iterator fetch_it = fetchBuffer.begin();
 203     std::list<FetchBlock*>::iterator end_it = fetchBuffer.end();
 204
 205     while (fetch_it != end_it) {
 206         if ((*fetch_it)->cnt == 0) {
 207             return fetch_it;
 208         } else {
 209             DPRINTF(InOrderCachePort, "Block %08p has %i insts pending.\n",
 210                     (*fetch_it)->addr, (*fetch_it)->cnt);
 211         }
 212         fetch_it++;
 213     }
 214
 215     return fetch_it;
 216 }
 217
 218 void
 219 FetchUnit::markBlockUsed(std::list<FetchBlock*>::iterator block_it)
 220 {
 221     // Move block from whatever location it is in fetch buffer
 222     // to the back (represents most-recently-used location)
 223     if (block_it != fetchBuffer.end()) {
 224         FetchBlock *mru_blk = *block_it;
 225         fetchBuffer.erase(block_it);
 226         fetchBuffer.push_back(mru_blk);
 227     }
 228 }
 229
 230 void
 231 FetchUnit::execute(int slot_num)
 232 {
 233     CacheReqPtr cache_req = dynamic_cast<CacheReqPtr>(reqs[slot_num]);
 234     assert(cache_req);
 235
 236     if (cachePortBlocked && cache_req->cmd == InitiateFetch) {
 237         DPRINTF(InOrderCachePort, "Cache Port Blocked. Cannot Access\n");
 238         cache_req->done(false);
 239         return;
 240     }
 241
 242     DynInstPtr inst = cache_req->inst;
 243     ThreadID tid = inst->readTid();
 244     Addr block_addr = cacheBlockAlign(inst->getMemAddr());
 245     int asid = cpu->asid[tid];
 246
 247     inst->fault = NoFault;
 248
 249     switch (cache_req->cmd)
 250     {
 251       case InitiateFetch:
 252         {
 253             // Check to see if we've already got this request buffered
 254             // or pending to be buffered
 255             bool do_fetch = true;
 256             std::list<FetchBlock*>::iterator pending_it;
 257             pending_it = findBlock(pendingFetch, asid, block_addr);
 258             if (pending_it != pendingFetch.end()) {
 259                 (*pending_it)->cnt++;
 260                 do_fetch = false;
 261
 262                 DPRINTF(InOrderCachePort, "%08p is a pending fetch block "
 263                         "(pending:%i).\n", block_addr,
 264                         (*pending_it)->cnt);
 265             } else if (pendingFetch.size() < fetchBuffSize) {
 266                 std::list<FetchBlock*>::iterator buff_it;
 267                 buff_it = findBlock(fetchBuffer, asid, block_addr);
 268                 if (buff_it  != fetchBuffer.end()) {
 269                     (*buff_it)->cnt++;
 270                     do_fetch = false;
 271
 272                     DPRINTF(InOrderCachePort, "%08p is in fetch buffer"
 273                             "(pending:%i).\n", block_addr, (*buff_it)->cnt);
 274                 }
 275             }
 276
 277             if (!do_fetch) {
 278                 DPRINTF(InOrderCachePort, "Inst. [sn:%i] marked to be filled "
 279                         "through fetch buffer.\n", inst->seqNum);
 280                 cache_req->fetchBufferFill = true;
 281                 cache_req->setCompleted(true);
 282                 return;
 283             }
 284
 285             // Check to see if there is room in the fetchbuffer for this instruction.
 286             // If not, block this request.
 287             if (pendingFetch.size() >= fetchBuffSize) {
 288                 DPRINTF(InOrderCachePort, "No room available in fetch buffer.\n");
 289                 cache_req->done();
 290                 return;
 291             }
 292
 293             doTLBAccess(inst, cache_req, cacheBlkSize, 0, TheISA::TLB::Execute);
 294
 295             if (inst->fault == NoFault) {
 296                 DPRINTF(InOrderCachePort,
 297                         "[tid:%u]: Initiating fetch access to %s for "
 298                         "addr:%#x (block:%#x)\n", tid, name(),
 299                         cache_req->inst->getMemAddr(), block_addr);
 300
 301                 cache_req->reqData = new uint8_t[cacheBlkSize];
 302
 303                 inst->setCurResSlot(slot_num);
 304
 305                 doCacheAccess(inst);
 306
 307                 if (cache_req->isMemAccPending()) {
 308                     pendingFetch.push_back(new FetchBlock(asid, block_addr));
 309                 }
 310             }
 311
 312             break;
 313         }
 314
 315       case CompleteFetch:
 316         if (cache_req->fetchBufferFill) {
 317             // Block request if it's depending on a previous fetch, but it hasnt made it yet
 318             std::list<FetchBlock*>::iterator fetch_it = findBlock(fetchBuffer, asid, block_addr);
 319             if (fetch_it == fetchBuffer.end()) {
 320                 DPRINTF(InOrderCachePort, "%#x not available yet\n",
 321                         block_addr);
 322                 cache_req->setCompleted(false);
 323                 return;
 324             }
 325
 326             // Make New Instruction
 327             createMachInst(fetch_it, inst);
 328             if (inst->traceData) {
 329                 inst->traceData->setStaticInst(inst->staticInst);
 330                 inst->traceData->setPC(inst->pcState());
 331             }
 332
 333             // FetchBuffer Book-Keeping
 334             (*fetch_it)->cnt--;
 335             assert((*fetch_it)->cnt >= 0);
 336             markBlockUsed(fetch_it);
 337
 338             cache_req->done();
 339             return;
 340         }
 341
 342         if (cache_req->isMemAccComplete()) {
 343             if (fetchBuffer.size() >= fetchBuffSize) {
 344                 // If there is no replacement block, then we'll just have
 345                 // to wait till that gets cleared before satisfying the fetch
 346                 // for this instruction
 347                 std::list<FetchBlock*>::iterator repl_it  =
 348                     findReplacementBlock();
 349                 if (repl_it == fetchBuffer.end()) {
 350                     DPRINTF(InOrderCachePort, "Unable to find replacement block"
 351                             " and complete fetch.\n");
 352                     cache_req->setCompleted(false);
 353                     return;
 354                 }
 355
 356                 delete [] (*repl_it)->block;
 357                 delete *repl_it;
 358                 fetchBuffer.erase(repl_it);
 359             }
 360
 361             DPRINTF(InOrderCachePort,
 362                     "[tid:%i]: Completing Fetch Access for [sn:%i]\n",
 363                     tid, inst->seqNum);
 364
 365             // Make New Instruction
 366             std::list<FetchBlock*>::iterator fetch_it  =
 367                 findBlock(pendingFetch, asid, block_addr);
 368
 369             assert(fetch_it != pendingFetch.end());
 370             assert((*fetch_it)->valid);
 371
 372             createMachInst(fetch_it, inst);
 373             if (inst->traceData) {
 374                 inst->traceData->setStaticInst(inst->staticInst);
 375                 inst->traceData->setPC(inst->pcState());
 376             }
 377
 378
 379             // Update instructions waiting on new fetch block
 380             FetchBlock *new_block = (*fetch_it);
 381             new_block->cnt--;
 382             assert(new_block->cnt >= 0);
 383
 384             // Finally, update FetchBuffer w/Pending Block into the
 385             // MRU location
 386             pendingFetch.erase(fetch_it);
 387             fetchBuffer.push_back(new_block);
 388
 389             DPRINTF(InOrderCachePort, "[tid:%i]: Instruction [sn:%i] is: %s\n",
 390                     tid, inst->seqNum,
 391                     inst->staticInst->disassemble(inst->instAddr()));
 392
 393             inst->unsetMemAddr();
 394
 395             delete cache_req->dataPkt;
 396
 397             cache_req->done();
 398         } else {
 399             DPRINTF(InOrderCachePort,
 400                      "[tid:%i]: [sn:%i]: Unable to Complete Fetch Access\n",
 401                     tid, inst->seqNum);
 402             DPRINTF(InOrderStall,
 403                     "STALL: [tid:%i]: Fetch miss from %08p\n",
 404                     tid, cache_req->inst->instAddr());
 405             cache_req->setCompleted(false);
 406             // NOTE: For SwitchOnCacheMiss ThreadModel, we *don't* switch on
 407             //       fetch miss, but we could ...
 408             // cache_req->setMemStall(true);
 409         }
 410         break;
 411
 412       default:
 413         fatal("Unrecognized command to %s", resName);
 414     }
 415 }
 416
 417 void
 418 FetchUnit::processCacheCompletion(PacketPtr pkt)
 419 {
 420     // Cast to correct packet type
 421     CacheReqPacket* cache_pkt = dynamic_cast<CacheReqPacket*>(pkt);
 422     assert(cache_pkt);
 423
 424     if (cache_pkt->cacheReq->isSquashed()) {
 425         DPRINTF(InOrderCachePort,
 426                 "Ignoring completion of squashed access, [tid:%i] [sn:%i]\n",
 427                 cache_pkt->cacheReq->getInst()->readTid(),
 428                 cache_pkt->cacheReq->getInst()->seqNum);
 429         DPRINTF(RefCount,
 430                 "Ignoring completion of squashed access, [tid:%i] [sn:%i]\n",
 431                 cache_pkt->cacheReq->getTid(),
 432                 cache_pkt->cacheReq->seqNum);
 433
 434         cache_pkt->cacheReq->done();
 435         cache_pkt->cacheReq->freeSlot();
 436         delete cache_pkt;
 437
 438         cpu->wakeCPU();
 439         return;
 440     }
 441
 442     Addr block_addr = cacheBlockAlign(cache_pkt->cacheReq->
 443                                       getInst()->getMemAddr());
 444
 445     DPRINTF(InOrderCachePort,
 446             "[tid:%u]: [sn:%i]: Waking from fetch access to addr:%#x(phys:%#x), size:%i\n",
 447             cache_pkt->cacheReq->getInst()->readTid(),
 448             cache_pkt->cacheReq->getInst()->seqNum,
 449             block_addr, cache_pkt->getAddr(), cache_pkt->getSize());
 450
 451     // Cast to correct request type
 452     CacheRequest *cache_req = dynamic_cast<CacheReqPtr>(
 453         findRequest(cache_pkt->cacheReq->getInst(), cache_pkt->instIdx));
 454
 455     if (!cache_req) {
 456         panic("[tid:%u]: [sn:%i]: Can't find slot for fetch access to "
 457               "addr. %08p\n", cache_pkt->cacheReq->getInst()->readTid(),
 458               cache_pkt->cacheReq->getInst()->seqNum,
 459               block_addr);
 460     }
 461
 462     // Get resource request info
 463     unsigned stage_num = cache_req->getStageNum();
 464     DynInstPtr inst = cache_req->inst;
 465     ThreadID tid = cache_req->inst->readTid();
 466     short asid = cpu->asid[tid];
 467
 468     assert(!cache_req->isSquashed());
 469     assert(inst->curSkedEntry->cmd == CompleteFetch);
 470
 471     DPRINTF(InOrderCachePort,
 472             "[tid:%u]: [sn:%i]: Processing fetch access for block %#x\n",
 473             tid, inst->seqNum, block_addr);
 474
 475     std::list<FetchBlock*>::iterator pend_it = findBlock(pendingFetch, asid,
 476                                                          block_addr);
 477     assert(pend_it != pendingFetch.end());
 478
 479     // Copy Data to pendingFetch queue...
 480     (*pend_it)->block = new uint8_t[cacheBlkSize];
 481     memcpy((*pend_it)->block, cache_pkt->getPtr<uint8_t>(), cacheBlkSize);
 482     (*pend_it)->valid = true;
 483
 484     cache_req->setMemAccPending(false);
 485     cache_req->setMemAccCompleted();
 486
 487     if (cache_req->isMemStall() &&
 488         cpu->threadModel == InOrderCPU::SwitchOnCacheMiss) {
 489         DPRINTF(InOrderCachePort, "[tid:%u] Waking up from Cache Miss.\n",
 490                 tid);
 491
 492         cpu->activateContext(tid);
 493
 494         DPRINTF(ThreadModel, "Activating [tid:%i] after return from cache"
 495                 "miss.\n", tid);
 496     }
 497
 498     // Wake up the CPU (if it went to sleep and was waiting on this
 499     // completion event).
 500     cpu->wakeCPU();
 501
 502     DPRINTF(Activity, "[tid:%u] Activating %s due to cache completion\n",
 503             tid, cpu->pipelineStage[stage_num]->name());
 504
 505     cpu->switchToActive(stage_num);
 506 }
 507
 508 void
 509 FetchUnit::squashCacheRequest(CacheReqPtr req_ptr)
 510 {
 511     DynInstPtr inst = req_ptr->getInst();
 512     ThreadID tid = inst->readTid();
 513     Addr block_addr = cacheBlockAlign(inst->getMemAddr());
 514     int asid = cpu->asid[tid];
 515
 516     // Check Fetch Buffer (or pending fetch) for this block and
 517     // update pending counts
 518     std::list<FetchBlock*>::iterator buff_it = findBlock(fetchBuffer,
 519                                                          asid,
 520                                                          block_addr);
 521     if (buff_it != fetchBuffer.end()) {
 522         (*buff_it)->cnt--;
 523         DPRINTF(InOrderCachePort, "[sn:%i] Removing Pending Fetch "
 524                 "for Buffer block %08p (cnt=%i)\n", inst->seqNum,
 525                 block_addr, (*buff_it)->cnt);
 526     } else {
 527         std::list<FetchBlock*>::iterator block_it = findBlock(pendingFetch,
 528                                                               asid,
 529                                                               block_addr);
 530         if (block_it != pendingFetch.end()) {
 531             (*block_it)->cnt--;
 532             if ((*block_it)->cnt == 0) {
 533                 DPRINTF(InOrderCachePort, "[sn:%i] Removing Pending Fetch "
 534                         "for block %08p (cnt=%i)\n", inst->seqNum,
 535                         block_addr, (*block_it)->cnt);
 536                 if ((*block_it)->block) {
 537                     delete [] (*block_it)->block;
 538                 }
 539                 delete *block_it;
 540                 pendingFetch.erase(block_it);
 541             }
 542         }
 543     }
 544
 545     CacheUnit::squashCacheRequest(req_ptr);
 546 }
 547