src/cpu/inorder/resources/fetch_unit.cc

   1 /*
   2  * Copyright (c) 2011 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #include <list>
  33 #include <vector>
  34
  35 #include "arch/isa_traits.hh"
  36 #include "arch/locked_mem.hh"
  37 #include "arch/predecoder.hh"
  38 #include "arch/utility.hh"
  39 #include "config/the_isa.hh"
  40 #include "cpu/inorder/resources/cache_unit.hh"
  41 #include "cpu/inorder/resources/fetch_unit.hh"
  42 #include "cpu/inorder/cpu.hh"
  43 #include "cpu/inorder/pipeline_traits.hh"
  44 #include "cpu/inorder/resource_pool.hh"
  45 #include "debug/Activity.hh"
  46 #include "debug/InOrderCachePort.hh"
  47 #include "debug/InOrderStall.hh"
  48 #include "debug/RefCount.hh"
  49 #include "debug/ThreadModel.hh"
  50 #include "mem/request.hh"
  51
  52 using namespace std;
  53 using namespace TheISA;
  54 using namespace ThePipeline;
  55
  56 FetchUnit::FetchUnit(string res_name, int res_id, int res_width,
  57                      int res_latency, InOrderCPU *_cpu,
  58                      ThePipeline::Params *params)
  59     : CacheUnit(res_name, res_id, res_width, res_latency, _cpu, params),
  60       instSize(sizeof(TheISA::MachInst)), fetchBuffSize(params->fetchBuffSize),
  61       predecoder(NULL)
  62 { }
  63
  64 FetchUnit::~FetchUnit()
  65 {
  66     std::list<FetchBlock*>::iterator fetch_it = fetchBuffer.begin();
  67     std::list<FetchBlock*>::iterator end_it = fetchBuffer.end();
  68     while (fetch_it != end_it) {
  69         delete (*fetch_it)->block;
  70         delete *fetch_it;
  71         fetch_it++;
  72     }
  73     fetchBuffer.clear();
  74
  75
  76     std::list<FetchBlock*>::iterator pend_it = pendingFetch.begin();
  77     std::list<FetchBlock*>::iterator pend_end = pendingFetch.end();
  78     while (pend_it != pend_end) {
  79         if ((*pend_it)->block) {
  80             delete (*pend_it)->block;
  81         }
  82
  83         delete *pend_it;
  84         pend_it++;
  85     }
  86     pendingFetch.clear();
  87 }
  88
  89 void
  90 FetchUnit::createMachInst(std::list<FetchBlock*>::iterator fetch_it,
  91                           DynInstPtr inst)
  92 {
  93     ExtMachInst ext_inst;
  94     Addr block_addr = cacheBlockAlign(inst->getMemAddr());
  95     Addr fetch_addr = inst->getMemAddr();
  96     unsigned fetch_offset = (fetch_addr - block_addr) / instSize;
  97     ThreadID tid = inst->readTid();
  98     TheISA::PCState instPC = inst->pcState();
  99
 100
 101     DPRINTF(InOrderCachePort, "Creating instruction [sn:%i] w/fetch data @"
 102             "addr:%08p block:%08p\n", inst->seqNum, fetch_addr, block_addr);
 103
 104     assert((*fetch_it)->valid);
 105
 106     TheISA::MachInst *fetchInsts =
 107         reinterpret_cast<TheISA::MachInst *>((*fetch_it)->block);
 108
 109     MachInst mach_inst =
 110         TheISA::gtoh(fetchInsts[fetch_offset]);
 111
 112     predecoder.setTC(cpu->thread[tid]->getTC());
 113     predecoder.moreBytes(instPC, inst->instAddr(), mach_inst);
 114     assert(predecoder.extMachInstReady());
 115     ext_inst = predecoder.getExtMachInst(instPC);
 116
 117     inst->pcState(instPC);
 118     inst->setMachInst(ext_inst);
 119 }
 120
 121 int
 122 FetchUnit::getSlot(DynInstPtr inst)
 123 {
 124     if (tlbBlocked[inst->threadNumber]) {
 125         return -1;
 126     }
 127
 128     if (!inst->validMemAddr()) {
 129         panic("[tid:%i][sn:%i] Mem. Addr. must be set before requesting "
 130               "cache access\n", inst->readTid(), inst->seqNum);
 131     }
 132
 133     int new_slot = Resource::getSlot(inst);
 134
 135     if (new_slot == -1)
 136         return -1;
 137
 138     inst->memTime = curTick();
 139     return new_slot;
 140 }
 141
 142 void
 143 FetchUnit::removeAddrDependency(DynInstPtr inst)
 144 {
 145     inst->unsetMemAddr();
 146 }
 147
 148 ResReqPtr
 149 FetchUnit::getRequest(DynInstPtr inst, int stage_num, int res_idx,
 150                      int slot_num, unsigned cmd)
 151 {
 152     ScheduleEntry* sched_entry = *inst->curSkedEntry;
 153     CacheRequest* cache_req = dynamic_cast<CacheRequest*>(reqs[slot_num]);
 154
 155     if (!inst->validMemAddr()) {
 156         panic("Mem. Addr. must be set before requesting cache access\n");
 157     }
 158
 159     assert(sched_entry->cmd == InitiateFetch);
 160
 161     DPRINTF(InOrderCachePort,
 162             "[tid:%i]: Fetch request from [sn:%i] for addr %08p\n",
 163             inst->readTid(), inst->seqNum, inst->getMemAddr());
 164
 165     cache_req->setRequest(inst, stage_num, id, slot_num,
 166                           sched_entry->cmd, MemCmd::ReadReq,
 167                           inst->curSkedEntry->idx);
 168
 169     return cache_req;
 170 }
 171
 172 void
 173 FetchUnit::setupMemRequest(DynInstPtr inst, CacheReqPtr cache_req,
 174                            int acc_size, int flags)
 175 {
 176     ThreadID tid = inst->readTid();
 177     Addr aligned_addr = cacheBlockAlign(inst->getMemAddr());
 178     if (cache_req->memReq == NULL) {
 179         cache_req->memReq =
 180             new Request(tid, aligned_addr, acc_size, flags,
 181                         inst->instAddr(), cpu->readCpuId(), tid);
 182         DPRINTF(InOrderCachePort, "[sn:%i] Created memReq @%x, ->%x\n",
 183                 inst->seqNum, &cache_req->memReq, cache_req->memReq);
 184     }
 185 }
 186
 187 std::list<FetchUnit::FetchBlock*>::iterator
 188 FetchUnit::findBlock(std::list<FetchBlock*> &fetch_blocks, int asid,
 189                      Addr block_addr)
 190 {
 191     std::list<FetchBlock*>::iterator fetch_it = fetch_blocks.begin();
 192     std::list<FetchBlock*>::iterator end_it = fetch_blocks.end();
 193
 194     while (fetch_it != end_it) {
 195         if ((*fetch_it)->asid == asid &&
 196             (*fetch_it)->addr == block_addr) {
 197             return fetch_it;
 198         }
 199
 200         fetch_it++;
 201     }
 202
 203     return fetch_it;
 204 }
 205
 206 std::list<FetchUnit::FetchBlock*>::iterator
 207 FetchUnit::findReplacementBlock()
 208 {
 209     std::list<FetchBlock*>::iterator fetch_it = fetchBuffer.begin();
 210     std::list<FetchBlock*>::iterator end_it = fetchBuffer.end();
 211
 212     while (fetch_it != end_it) {
 213         if ((*fetch_it)->cnt == 0) {
 214             return fetch_it;
 215         } else {
 216             DPRINTF(InOrderCachePort, "Block %08p has %i insts pending.\n",
 217                     (*fetch_it)->addr, (*fetch_it)->cnt);
 218         }
 219         fetch_it++;
 220     }
 221
 222     return fetch_it;
 223 }
 224
 225 void
 226 FetchUnit::markBlockUsed(std::list<FetchBlock*>::iterator block_it)
 227 {
 228     // Move block from whatever location it is in fetch buffer
 229     // to the back (represents most-recently-used location)
 230     if (block_it != fetchBuffer.end()) {
 231         FetchBlock *mru_blk = *block_it;
 232         fetchBuffer.erase(block_it);
 233         fetchBuffer.push_back(mru_blk);
 234     }
 235 }
 236
 237 int
 238 FetchUnit::blocksInUse()
 239 {
 240     std::list<FetchBlock*>::iterator fetch_it = fetchBuffer.begin();
 241     std::list<FetchBlock*>::iterator end_it = fetchBuffer.end();
 242
 243     int cnt = 0;
 244     while (fetch_it != end_it) {
 245         if ((*fetch_it)->cnt > 0)
 246             cnt++;
 247
 248         fetch_it++;
 249     }
 250
 251     return cnt;
 252 }
 253
 254 void
 255 FetchUnit::execute(int slot_num)
 256 {
 257     CacheReqPtr cache_req = dynamic_cast<CacheReqPtr>(reqs[slot_num]);
 258     assert(cache_req);
 259
 260     if (cachePortBlocked && cache_req->cmd == InitiateFetch) {
 261         DPRINTF(InOrderCachePort, "Cache Port Blocked. Cannot Access\n");
 262         cache_req->done(false);
 263         return;
 264     }
 265
 266     DynInstPtr inst = cache_req->inst;
 267     ThreadID tid = inst->readTid();
 268     Addr block_addr = cacheBlockAlign(inst->getMemAddr());
 269     int asid = cpu->asid[tid];
 270
 271     inst->fault = NoFault;
 272
 273     switch (cache_req->cmd)
 274     {
 275       case InitiateFetch:
 276         {
 277             // Check to see if we've already got this request buffered
 278             // or pending to be buffered
 279             bool do_fetch = true;
 280             int total_pending = pendingFetch.size() + blocksInUse();
 281
 282             std::list<FetchBlock*>::iterator pending_it;
 283             pending_it = findBlock(pendingFetch, asid, block_addr);
 284             if (pending_it != pendingFetch.end()) {
 285                 (*pending_it)->cnt++;
 286                 do_fetch = false;
 287
 288                 DPRINTF(InOrderCachePort, "%08p is a pending fetch block "
 289                         "(pending:%i).\n", block_addr,
 290                         (*pending_it)->cnt);
 291             } else if (total_pending < fetchBuffSize) {
 292                 std::list<FetchBlock*>::iterator buff_it;
 293                 buff_it = findBlock(fetchBuffer, asid, block_addr);
 294                 if (buff_it != fetchBuffer.end()) {
 295                     (*buff_it)->cnt++;
 296                     do_fetch = false;
 297
 298                     DPRINTF(InOrderCachePort, "%08p is in fetch buffer "
 299                             "(pending:%i).\n", block_addr, (*buff_it)->cnt);
 300                 }
 301             }
 302
 303             if (!do_fetch) {
 304                 DPRINTF(InOrderCachePort, "Inst. [sn:%i] marked to be filled "
 305                         "through fetch buffer.\n", inst->seqNum);
 306                 cache_req->fetchBufferFill = true;
 307                 cache_req->setCompleted(true);
 308                 return;
 309             }
 310
 311             // Check to see if there is room in the fetchbuffer for this instruction.
 312             // If not, block this request.
 313             if (total_pending >= fetchBuffSize) {
 314                 DPRINTF(InOrderCachePort, "No room available in fetch buffer.\n");
 315                 cache_req->done(false);
 316                 return;
 317             }
 318
 319             doTLBAccess(inst, cache_req, cacheBlkSize, 0, TheISA::TLB::Execute);
 320
 321             if (inst->fault == NoFault) {
 322                 DPRINTF(InOrderCachePort,
 323                         "[tid:%u]: Initiating fetch access to %s for "
 324                         "addr:%#x (block:%#x)\n", tid, name(),
 325                         cache_req->inst->getMemAddr(), block_addr);
 326
 327                 cache_req->reqData = new uint8_t[cacheBlkSize];
 328
 329                 inst->setCurResSlot(slot_num);
 330
 331                 doCacheAccess(inst);
 332
 333                 if (cache_req->isMemAccPending()) {
 334                     pendingFetch.push_back(new FetchBlock(asid, block_addr));
 335
 336                     // mark replacement block
 337                 }
 338             }
 339
 340             break;
 341         }
 342
 343       case CompleteFetch:
 344         if (cache_req->fetchBufferFill) {
 345             // Block request if it's depending on a previous fetch, but it hasnt made it yet
 346             std::list<FetchBlock*>::iterator fetch_it = findBlock(fetchBuffer, asid, block_addr);
 347             if (fetch_it == fetchBuffer.end()) {
 348                 DPRINTF(InOrderCachePort, "%#x not available yet\n",
 349                         block_addr);
 350                 cache_req->setCompleted(false);
 351                 return;
 352             }
 353
 354             // Make New Instruction
 355             createMachInst(fetch_it, inst);
 356             if (inst->traceData) {
 357                 inst->traceData->setStaticInst(inst->staticInst);
 358                 inst->traceData->setPC(inst->pcState());
 359             }
 360
 361             // FetchBuffer Book-Keeping
 362             (*fetch_it)->cnt--;
 363             assert((*fetch_it)->cnt >= 0);
 364             markBlockUsed(fetch_it);
 365
 366             cache_req->done();
 367             return;
 368         }
 369
 370         if (cache_req->isMemAccComplete()) {
 371             if (fetchBuffer.size() >= fetchBuffSize) {
 372                 // If there is no replacement block, then we'll just have
 373                 // to wait till that gets cleared before satisfying the fetch
 374                 // for this instruction
 375                 std::list<FetchBlock*>::iterator repl_it  =
 376                     findReplacementBlock();
 377                 if (repl_it == fetchBuffer.end()) {
 378                     DPRINTF(InOrderCachePort, "Unable to find replacement block"
 379                             " and complete fetch.\n");
 380                     cache_req->setCompleted(false);
 381                     return;
 382                 }
 383
 384                 delete [] (*repl_it)->block;
 385                 delete *repl_it;
 386                 fetchBuffer.erase(repl_it);
 387             }
 388
 389             DPRINTF(InOrderCachePort,
 390                     "[tid:%i]: Completing Fetch Access for [sn:%i]\n",
 391                     tid, inst->seqNum);
 392
 393             // Make New Instruction
 394             std::list<FetchBlock*>::iterator fetch_it  =
 395                 findBlock(pendingFetch, asid, block_addr);
 396
 397             assert(fetch_it != pendingFetch.end());
 398             assert((*fetch_it)->valid);
 399
 400             createMachInst(fetch_it, inst);
 401             if (inst->traceData) {
 402                 inst->traceData->setStaticInst(inst->staticInst);
 403                 inst->traceData->setPC(inst->pcState());
 404             }
 405
 406
 407             // Update instructions waiting on new fetch block
 408             FetchBlock *new_block = (*fetch_it);
 409             new_block->cnt--;
 410             assert(new_block->cnt >= 0);
 411
 412             // Finally, update FetchBuffer w/Pending Block into the
 413             // MRU location
 414             pendingFetch.erase(fetch_it);
 415             fetchBuffer.push_back(new_block);
 416
 417             DPRINTF(InOrderCachePort, "[tid:%i]: Instruction [sn:%i] is: %s\n",
 418                     tid, inst->seqNum,
 419                     inst->staticInst->disassemble(inst->instAddr()));
 420
 421             inst->unsetMemAddr();
 422
 423             cache_req->done();
 424         } else {
 425             DPRINTF(InOrderCachePort,
 426                      "[tid:%i]: [sn:%i]: Unable to Complete Fetch Access\n",
 427                     tid, inst->seqNum);
 428             DPRINTF(InOrderStall,
 429                     "STALL: [tid:%i]: Fetch miss from %08p\n",
 430                     tid, cache_req->inst->instAddr());
 431             cache_req->setCompleted(false);
 432             // NOTE: For SwitchOnCacheMiss ThreadModel, we *don't* switch on
 433             //       fetch miss, but we could ...
 434             // cache_req->setMemStall(true);
 435         }
 436         break;
 437
 438       default:
 439         fatal("Unrecognized command to %s", resName);
 440     }
 441 }
 442
 443 void
 444 FetchUnit::processCacheCompletion(PacketPtr pkt)
 445 {
 446     // Cast to correct packet type
 447     CacheReqPacket* cache_pkt = dynamic_cast<CacheReqPacket*>(pkt);
 448     assert(cache_pkt);
 449
 450     DPRINTF(InOrderCachePort, "Finished request for %x\n",
 451             cache_pkt->getAddr());
 452
 453     if (processSquash(cache_pkt))
 454         return;
 455
 456     Addr block_addr = cacheBlockAlign(cache_pkt->cacheReq->
 457                                       getInst()->getMemAddr());
 458
 459     DPRINTF(InOrderCachePort,
 460             "[tid:%u]: [sn:%i]: Waking from fetch access to addr:%#x(phys:%#x), size:%i\n",
 461             cache_pkt->cacheReq->getInst()->readTid(),
 462             cache_pkt->cacheReq->getInst()->seqNum,
 463             block_addr, cache_pkt->getAddr(), cache_pkt->getSize());
 464
 465     // Cast to correct request type
 466     CacheRequest *cache_req = dynamic_cast<CacheReqPtr>(
 467         findRequest(cache_pkt->cacheReq->getInst(), cache_pkt->instIdx));
 468
 469     if (!cache_req) {
 470         panic("[tid:%u]: [sn:%i]: Can't find slot for fetch access to "
 471               "addr. %08p\n", cache_pkt->cacheReq->getInst()->readTid(),
 472               cache_pkt->cacheReq->getInst()->seqNum,
 473               block_addr);
 474     }
 475
 476     // Get resource request info
 477     unsigned stage_num = cache_req->getStageNum();
 478     DynInstPtr inst = cache_req->inst;
 479     ThreadID tid = cache_req->inst->readTid();
 480     short asid = cpu->asid[tid];
 481
 482     assert(!cache_req->isSquashed());
 483     assert(inst->curSkedEntry->cmd == CompleteFetch);
 484
 485     DPRINTF(InOrderCachePort,
 486             "[tid:%u]: [sn:%i]: Processing fetch access for block %#x\n",
 487             tid, inst->seqNum, block_addr);
 488
 489     std::list<FetchBlock*>::iterator pend_it = findBlock(pendingFetch, asid,
 490                                                          block_addr);
 491     assert(pend_it != pendingFetch.end());
 492
 493     // Copy Data to pendingFetch queue...
 494     (*pend_it)->block = new uint8_t[cacheBlkSize];
 495     memcpy((*pend_it)->block, cache_pkt->getPtr<uint8_t>(), cacheBlkSize);
 496     (*pend_it)->valid = true;
 497
 498     cache_req->setMemAccPending(false);
 499     cache_req->setMemAccCompleted();
 500
 501     if (cache_req->isMemStall() &&
 502         cpu->threadModel == InOrderCPU::SwitchOnCacheMiss) {
 503         DPRINTF(InOrderCachePort, "[tid:%u] Waking up from Cache Miss.\n",
 504                 tid);
 505
 506         cpu->activateContext(tid);
 507
 508         DPRINTF(ThreadModel, "Activating [tid:%i] after return from cache"
 509                 "miss.\n", tid);
 510     }
 511
 512     // Wake up the CPU (if it went to sleep and was waiting on this
 513     // completion event).
 514     cpu->wakeCPU();
 515
 516     DPRINTF(Activity, "[tid:%u] Activating %s due to cache completion\n",
 517             tid, cpu->pipelineStage[stage_num]->name());
 518
 519     cpu->switchToActive(stage_num);
 520 }
 521
 522 void
 523 FetchUnit::squashCacheRequest(CacheReqPtr req_ptr)
 524 {
 525     DynInstPtr inst = req_ptr->getInst();
 526     ThreadID tid = inst->readTid();
 527     Addr block_addr = cacheBlockAlign(inst->getMemAddr());
 528     int asid = cpu->asid[tid];
 529
 530     // Check Fetch Buffer (or pending fetch) for this block and
 531     // update pending counts
 532     std::list<FetchBlock*>::iterator buff_it = findBlock(fetchBuffer,
 533                                                          asid,
 534                                                          block_addr);
 535     if (buff_it != fetchBuffer.end()) {
 536         (*buff_it)->cnt--;
 537         DPRINTF(InOrderCachePort, "[sn:%i] Removing Pending Access "
 538                 "for Fetch Buffer block %08p (cnt=%i)\n", inst->seqNum,
 539                 block_addr, (*buff_it)->cnt);
 540         assert((*buff_it)->cnt >= 0);
 541     } else {
 542         std::list<FetchBlock*>::iterator block_it = findBlock(pendingFetch,
 543                                                               asid,
 544                                                               block_addr);
 545         if (block_it != pendingFetch.end()) {
 546             (*block_it)->cnt--;
 547             DPRINTF(InOrderCachePort, "[sn:%i] Removing Pending Access "
 548                     "for Pending Buffer Block %08p (cnt=%i)\n",
 549                     inst->seqNum,
 550                     block_addr, (*block_it)->cnt);
 551             assert((*block_it)->cnt >= 0);
 552             if ((*block_it)->cnt == 0) {
 553                 if ((*block_it)->block) {
 554                     delete [] (*block_it)->block;
 555                 }
 556                 delete *block_it;
 557                 pendingFetch.erase(block_it);
 558             }
 559         }
 560     }
 561
 562     CacheUnit::squashCacheRequest(req_ptr);
 563 }
 564
 565 void
 566 FetchUnit::trap(Fault fault, ThreadID tid, DynInstPtr inst)
 567 {
 568     //@todo: per thread?
 569     predecoder.reset();
 570 }