2 * Copyright (c) 2011 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Korey Sewell
35 #include "arch/isa_traits.hh"
36 #include "arch/locked_mem.hh"
37 #include "arch/utility.hh"
38 #include "arch/predecoder.hh"
39 #include "config/the_isa.hh"
40 #include "cpu/inorder/resources/cache_unit.hh"
41 #include "cpu/inorder/resources/fetch_unit.hh"
42 #include "cpu/inorder/pipeline_traits.hh"
43 #include "cpu/inorder/cpu.hh"
44 #include "cpu/inorder/resource_pool.hh"
45 #include "mem/request.hh"
48 using namespace TheISA
;
49 using namespace ThePipeline
;
51 FetchUnit::FetchUnit(string res_name
, int res_id
, int res_width
,
52 int res_latency
, InOrderCPU
*_cpu
,
53 ThePipeline::Params
*params
)
54 : CacheUnit(res_name
, res_id
, res_width
, res_latency
, _cpu
, params
),
55 instSize(sizeof(TheISA::MachInst
)), fetchBuffSize(params
->fetchBuffSize
),
59 FetchUnit::~FetchUnit()
61 std::list
<FetchBlock
*>::iterator fetch_it
= fetchBuffer
.begin();
62 std::list
<FetchBlock
*>::iterator end_it
= fetchBuffer
.end();
63 while (fetch_it
!= end_it
) {
64 delete (*fetch_it
)->block
;
71 std::list
<FetchBlock
*>::iterator pend_it
= pendingFetch
.begin();
72 std::list
<FetchBlock
*>::iterator pend_end
= pendingFetch
.end();
73 while (pend_it
!= pend_end
) {
74 if ((*pend_it
)->block
) {
75 delete (*pend_it
)->block
;
85 FetchUnit::createMachInst(std::list
<FetchBlock
*>::iterator fetch_it
,
89 Addr block_addr
= cacheBlockAlign(inst
->getMemAddr());
90 Addr fetch_addr
= inst
->getMemAddr();
91 unsigned fetch_offset
= (fetch_addr
- block_addr
) / instSize
;
92 ThreadID tid
= inst
->readTid();
93 TheISA::PCState instPC
= inst
->pcState();
96 DPRINTF(InOrderCachePort
, "Creating instruction [sn:%i] w/fetch data @"
97 "addr:%08p block:%08p\n", inst
->seqNum
, fetch_addr
, block_addr
);
99 assert((*fetch_it
)->valid
);
101 TheISA::MachInst
*fetchInsts
=
102 reinterpret_cast<TheISA::MachInst
*>((*fetch_it
)->block
);
105 TheISA::gtoh(fetchInsts
[fetch_offset
]);
107 predecoder
.setTC(cpu
->thread
[tid
]->getTC());
108 predecoder
.moreBytes(instPC
, inst
->instAddr(), mach_inst
);
109 ext_inst
= predecoder
.getExtMachInst(instPC
);
111 inst
->pcState(instPC
);
112 inst
->setMachInst(ext_inst
);
116 FetchUnit::getSlot(DynInstPtr inst
)
118 if (tlbBlocked
[inst
->threadNumber
]) {
122 if (!inst
->validMemAddr()) {
123 panic("[tid:%i][sn:%i] Mem. Addr. must be set before requesting "
124 "cache access\n", inst
->readTid(), inst
->seqNum
);
127 int new_slot
= Resource::getSlot(inst
);
132 inst
->memTime
= curTick();
137 FetchUnit::removeAddrDependency(DynInstPtr inst
)
139 inst
->unsetMemAddr();
143 FetchUnit::getRequest(DynInstPtr inst
, int stage_num
, int res_idx
,
144 int slot_num
, unsigned cmd
)
146 ScheduleEntry
* sched_entry
= *inst
->curSkedEntry
;
147 CacheRequest
* cache_req
= dynamic_cast<CacheRequest
*>(reqs
[slot_num
]);
149 if (!inst
->validMemAddr()) {
150 panic("Mem. Addr. must be set before requesting cache access\n");
153 assert(sched_entry
->cmd
== InitiateFetch
);
155 DPRINTF(InOrderCachePort
,
156 "[tid:%i]: Fetch request from [sn:%i] for addr %08p\n",
157 inst
->readTid(), inst
->seqNum
, inst
->getMemAddr());
159 cache_req
->setRequest(inst
, stage_num
, id
, slot_num
,
160 sched_entry
->cmd
, MemCmd::ReadReq
,
161 inst
->curSkedEntry
->idx
);
167 FetchUnit::setupMemRequest(DynInstPtr inst
, CacheReqPtr cache_req
,
168 int acc_size
, int flags
)
170 ThreadID tid
= inst
->readTid();
171 Addr aligned_addr
= cacheBlockAlign(inst
->getMemAddr());
173 if (inst
->fetchMemReq
== NULL
)
175 new Request(tid
, aligned_addr
, acc_size
, flags
,
176 inst
->instAddr(), cpu
->readCpuId(), tid
);
179 cache_req
->memReq
= inst
->fetchMemReq
;
182 std::list
<FetchUnit::FetchBlock
*>::iterator
183 FetchUnit::findBlock(std::list
<FetchBlock
*> &fetch_blocks
, int asid
,
186 std::list
<FetchBlock
*>::iterator fetch_it
= fetch_blocks
.begin();
187 std::list
<FetchBlock
*>::iterator end_it
= fetch_blocks
.end();
189 while (fetch_it
!= end_it
) {
190 if ((*fetch_it
)->asid
== asid
&&
191 (*fetch_it
)->addr
== block_addr
) {
201 std::list
<FetchUnit::FetchBlock
*>::iterator
202 FetchUnit::findReplacementBlock()
204 std::list
<FetchBlock
*>::iterator fetch_it
= fetchBuffer
.begin();
205 std::list
<FetchBlock
*>::iterator end_it
= fetchBuffer
.end();
207 while (fetch_it
!= end_it
) {
208 if ((*fetch_it
)->cnt
== 0) {
211 DPRINTF(InOrderCachePort
, "Block %08p has %i insts pending.\n",
212 (*fetch_it
)->addr
, (*fetch_it
)->cnt
);
221 FetchUnit::markBlockUsed(std::list
<FetchBlock
*>::iterator block_it
)
223 // Move block from whatever location it is in fetch buffer
224 // to the back (represents most-recently-used location)
225 if (block_it
!= fetchBuffer
.end()) {
226 FetchBlock
*mru_blk
= *block_it
;
227 fetchBuffer
.erase(block_it
);
228 fetchBuffer
.push_back(mru_blk
);
233 FetchUnit::execute(int slot_num
)
235 CacheReqPtr cache_req
= dynamic_cast<CacheReqPtr
>(reqs
[slot_num
]);
238 if (cachePortBlocked
&& cache_req
->cmd
== InitiateFetch
) {
239 DPRINTF(InOrderCachePort
, "Cache Port Blocked. Cannot Access\n");
240 cache_req
->done(false);
244 DynInstPtr inst
= cache_req
->inst
;
245 ThreadID tid
= inst
->readTid();
246 Addr block_addr
= cacheBlockAlign(inst
->getMemAddr());
247 int asid
= cpu
->asid
[tid
];
249 inst
->fault
= NoFault
;
251 switch (cache_req
->cmd
)
255 // Check to see if we've already got this request buffered
256 // or pending to be buffered
257 bool do_fetch
= true;
258 std::list
<FetchBlock
*>::iterator pending_it
;
259 pending_it
= findBlock(pendingFetch
, asid
, block_addr
);
260 if (pending_it
!= pendingFetch
.end()) {
261 (*pending_it
)->cnt
++;
264 DPRINTF(InOrderCachePort
, "%08p is a pending fetch block "
265 "(pending:%i).\n", block_addr
,
267 } else if (pendingFetch
.size() < fetchBuffSize
) {
268 std::list
<FetchBlock
*>::iterator buff_it
;
269 buff_it
= findBlock(fetchBuffer
, asid
, block_addr
);
270 if (buff_it
!= fetchBuffer
.end()) {
274 DPRINTF(InOrderCachePort
, "%08p is in fetch buffer"
275 "(pending:%i).\n", block_addr
, (*buff_it
)->cnt
);
280 DPRINTF(InOrderCachePort
, "Inst. [sn:%i] marked to be filled "
281 "through fetch buffer.\n", inst
->seqNum
);
282 cache_req
->fetchBufferFill
= true;
283 cache_req
->setCompleted(true);
287 // Check to see if there is room in the fetchbuffer for this instruction.
288 // If not, block this request.
289 if (pendingFetch
.size() >= fetchBuffSize
) {
290 DPRINTF(InOrderCachePort
, "No room available in fetch buffer.\n");
295 doTLBAccess(inst
, cache_req
, cacheBlkSize
, 0, TheISA::TLB::Execute
);
297 if (inst
->fault
== NoFault
) {
298 DPRINTF(InOrderCachePort
,
299 "[tid:%u]: Initiating fetch access to %s for "
300 "addr:%#x (block:%#x)\n", tid
, name(),
301 cache_req
->inst
->getMemAddr(), block_addr
);
303 cache_req
->reqData
= new uint8_t[cacheBlkSize
];
305 inst
->setCurResSlot(slot_num
);
309 if (cache_req
->isMemAccPending()) {
310 pendingFetch
.push_back(new FetchBlock(asid
, block_addr
));
318 if (cache_req
->fetchBufferFill
) {
319 // Block request if it's depending on a previous fetch, but it hasnt made it yet
320 std::list
<FetchBlock
*>::iterator fetch_it
= findBlock(fetchBuffer
, asid
, block_addr
);
321 if (fetch_it
== fetchBuffer
.end()) {
322 DPRINTF(InOrderCachePort
, "%#x not available yet\n",
324 cache_req
->setCompleted(false);
328 // Make New Instruction
329 createMachInst(fetch_it
, inst
);
330 if (inst
->traceData
) {
331 inst
->traceData
->setStaticInst(inst
->staticInst
);
332 inst
->traceData
->setPC(inst
->pcState());
335 // FetchBuffer Book-Keeping
337 assert((*fetch_it
)->cnt
>= 0);
338 markBlockUsed(fetch_it
);
344 if (cache_req
->isMemAccComplete()) {
345 if (fetchBuffer
.size() >= fetchBuffSize
) {
346 // If there is no replacement block, then we'll just have
347 // to wait till that gets cleared before satisfying the fetch
348 // for this instruction
349 std::list
<FetchBlock
*>::iterator repl_it
=
350 findReplacementBlock();
351 if (repl_it
== fetchBuffer
.end()) {
352 DPRINTF(InOrderCachePort
, "Unable to find replacement block"
353 " and complete fetch.\n");
354 cache_req
->setCompleted(false);
358 delete [] (*repl_it
)->block
;
360 fetchBuffer
.erase(repl_it
);
363 DPRINTF(InOrderCachePort
,
364 "[tid:%i]: Completing Fetch Access for [sn:%i]\n",
367 // Make New Instruction
368 std::list
<FetchBlock
*>::iterator fetch_it
=
369 findBlock(pendingFetch
, asid
, block_addr
);
371 assert(fetch_it
!= pendingFetch
.end());
372 assert((*fetch_it
)->valid
);
374 createMachInst(fetch_it
, inst
);
375 if (inst
->traceData
) {
376 inst
->traceData
->setStaticInst(inst
->staticInst
);
377 inst
->traceData
->setPC(inst
->pcState());
381 // Update instructions waiting on new fetch block
382 FetchBlock
*new_block
= (*fetch_it
);
384 assert(new_block
->cnt
>= 0);
386 // Finally, update FetchBuffer w/Pending Block into the
388 pendingFetch
.erase(fetch_it
);
389 fetchBuffer
.push_back(new_block
);
391 DPRINTF(InOrderCachePort
, "[tid:%i]: Instruction [sn:%i] is: %s\n",
393 inst
->staticInst
->disassemble(inst
->instAddr()));
395 inst
->unsetMemAddr();
397 delete cache_req
->dataPkt
;
401 DPRINTF(InOrderCachePort
,
402 "[tid:%i]: [sn:%i]: Unable to Complete Fetch Access\n",
404 DPRINTF(InOrderStall
,
405 "STALL: [tid:%i]: Fetch miss from %08p\n",
406 tid
, cache_req
->inst
->instAddr());
407 cache_req
->setCompleted(false);
408 // NOTE: For SwitchOnCacheMiss ThreadModel, we *don't* switch on
409 // fetch miss, but we could ...
410 // cache_req->setMemStall(true);
415 fatal("Unrecognized command to %s", resName
);
420 FetchUnit::processCacheCompletion(PacketPtr pkt
)
422 // Cast to correct packet type
423 CacheReqPacket
* cache_pkt
= dynamic_cast<CacheReqPacket
*>(pkt
);
426 if (cache_pkt
->cacheReq
->isSquashed()) {
427 DPRINTF(InOrderCachePort
,
428 "Ignoring completion of squashed access, [tid:%i] [sn:%i]\n",
429 cache_pkt
->cacheReq
->getInst()->readTid(),
430 cache_pkt
->cacheReq
->getInst()->seqNum
);
432 "Ignoring completion of squashed access, [tid:%i] [sn:%i]\n",
433 cache_pkt
->cacheReq
->getTid(),
434 cache_pkt
->cacheReq
->seqNum
);
436 cache_pkt
->cacheReq
->done();
437 cache_pkt
->cacheReq
->freeSlot();
444 Addr block_addr
= cacheBlockAlign(cache_pkt
->cacheReq
->
445 getInst()->getMemAddr());
447 DPRINTF(InOrderCachePort
,
448 "[tid:%u]: [sn:%i]: Waking from fetch access to addr:%#x(phys:%#x), size:%i\n",
449 cache_pkt
->cacheReq
->getInst()->readTid(),
450 cache_pkt
->cacheReq
->getInst()->seqNum
,
451 block_addr
, cache_pkt
->getAddr(), cache_pkt
->getSize());
453 // Cast to correct request type
454 CacheRequest
*cache_req
= dynamic_cast<CacheReqPtr
>(
455 findRequest(cache_pkt
->cacheReq
->getInst(), cache_pkt
->instIdx
));
458 panic("[tid:%u]: [sn:%i]: Can't find slot for fetch access to "
459 "addr. %08p\n", cache_pkt
->cacheReq
->getInst()->readTid(),
460 cache_pkt
->cacheReq
->getInst()->seqNum
,
464 // Get resource request info
465 unsigned stage_num
= cache_req
->getStageNum();
466 DynInstPtr inst
= cache_req
->inst
;
467 ThreadID tid
= cache_req
->inst
->readTid();
468 short asid
= cpu
->asid
[tid
];
470 assert(!cache_req
->isSquashed());
471 assert(inst
->curSkedEntry
->cmd
== CompleteFetch
);
473 DPRINTF(InOrderCachePort
,
474 "[tid:%u]: [sn:%i]: Processing fetch access for block %#x\n",
475 tid
, inst
->seqNum
, block_addr
);
477 std::list
<FetchBlock
*>::iterator pend_it
= findBlock(pendingFetch
, asid
,
479 assert(pend_it
!= pendingFetch
.end());
481 // Copy Data to pendingFetch queue...
482 (*pend_it
)->block
= new uint8_t[cacheBlkSize
];
483 memcpy((*pend_it
)->block
, cache_pkt
->getPtr
<uint8_t>(), cacheBlkSize
);
484 (*pend_it
)->valid
= true;
486 cache_req
->setMemAccPending(false);
487 cache_req
->setMemAccCompleted();
489 if (cache_req
->isMemStall() &&
490 cpu
->threadModel
== InOrderCPU::SwitchOnCacheMiss
) {
491 DPRINTF(InOrderCachePort
, "[tid:%u] Waking up from Cache Miss.\n",
494 cpu
->activateContext(tid
);
496 DPRINTF(ThreadModel
, "Activating [tid:%i] after return from cache"
500 // Wake up the CPU (if it went to sleep and was waiting on this
501 // completion event).
504 DPRINTF(Activity
, "[tid:%u] Activating %s due to cache completion\n",
505 tid
, cpu
->pipelineStage
[stage_num
]->name());
507 cpu
->switchToActive(stage_num
);
511 FetchUnit::squashCacheRequest(CacheReqPtr req_ptr
)
513 DynInstPtr inst
= req_ptr
->getInst();
514 ThreadID tid
= inst
->readTid();
515 Addr block_addr
= cacheBlockAlign(inst
->getMemAddr());
516 int asid
= cpu
->asid
[tid
];
518 // Check Fetch Buffer (or pending fetch) for this block and
519 // update pending counts
520 std::list
<FetchBlock
*>::iterator buff_it
= findBlock(fetchBuffer
,
523 if (buff_it
!= fetchBuffer
.end()) {
525 DPRINTF(InOrderCachePort
, "[sn:%i] Removing Pending Fetch "
526 "for Buffer block %08p (cnt=%i)\n", inst
->seqNum
,
527 block_addr
, (*buff_it
)->cnt
);
529 std::list
<FetchBlock
*>::iterator block_it
= findBlock(pendingFetch
,
532 if (block_it
!= pendingFetch
.end()) {
534 if ((*block_it
)->cnt
== 0) {
535 DPRINTF(InOrderCachePort
, "[sn:%i] Removing Pending Fetch "
536 "for block %08p (cnt=%i)\n", inst
->seqNum
,
537 block_addr
, (*block_it
)->cnt
);
538 if ((*block_it
)->block
) {
539 delete [] (*block_it
)->block
;
542 pendingFetch
.erase(block_it
);
547 CacheUnit::squashCacheRequest(req_ptr
);