2 * Copyright (c) 2011 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Korey Sewell
35 #include "arch/isa_traits.hh"
36 #include "arch/locked_mem.hh"
37 #include "arch/utility.hh"
38 #include "arch/predecoder.hh"
39 #include "config/the_isa.hh"
40 #include "cpu/inorder/resources/cache_unit.hh"
41 #include "cpu/inorder/resources/fetch_unit.hh"
42 #include "cpu/inorder/pipeline_traits.hh"
43 #include "cpu/inorder/cpu.hh"
44 #include "cpu/inorder/resource_pool.hh"
45 #include "mem/request.hh"
48 using namespace TheISA
;
49 using namespace ThePipeline
;
51 FetchUnit::FetchUnit(string res_name
, int res_id
, int res_width
,
52 int res_latency
, InOrderCPU
*_cpu
,
53 ThePipeline::Params
*params
)
54 : CacheUnit(res_name
, res_id
, res_width
, res_latency
, _cpu
, params
),
55 instSize(sizeof(TheISA::MachInst
)), fetchBuffSize(params
->fetchBuffSize
),
60 FetchUnit::createMachInst(std::list
<FetchBlock
*>::iterator fetch_it
,
64 Addr block_addr
= cacheBlockAlign(inst
->getMemAddr());
65 Addr fetch_addr
= inst
->getMemAddr();
66 unsigned fetch_offset
= (fetch_addr
- block_addr
) / instSize
;
67 ThreadID tid
= inst
->readTid();
68 TheISA::PCState instPC
= inst
->pcState();
71 DPRINTF(InOrderCachePort
, "Creating instruction [sn:%i] w/fetch data @"
72 "addr:%08p block:%08p\n", inst
->seqNum
, fetch_addr
, block_addr
);
74 assert((*fetch_it
)->valid
);
76 TheISA::MachInst
*fetchInsts
=
77 reinterpret_cast<TheISA::MachInst
*>((*fetch_it
)->block
);
80 TheISA::gtoh(fetchInsts
[fetch_offset
]);
82 predecoder
.setTC(cpu
->thread
[tid
]->getTC());
83 predecoder
.moreBytes(instPC
, inst
->instAddr(), mach_inst
);
84 ext_inst
= predecoder
.getExtMachInst(instPC
);
86 inst
->pcState(instPC
);
87 inst
->setMachInst(ext_inst
);
91 FetchUnit::getSlot(DynInstPtr inst
)
93 if (tlbBlocked
[inst
->threadNumber
]) {
97 if (!inst
->validMemAddr()) {
98 panic("[tid:%i][sn:%i] Mem. Addr. must be set before requesting "
99 "cache access\n", inst
->readTid(), inst
->seqNum
);
102 int new_slot
= Resource::getSlot(inst
);
107 inst
->memTime
= curTick();
112 FetchUnit::removeAddrDependency(DynInstPtr inst
)
114 inst
->unsetMemAddr();
118 FetchUnit::getRequest(DynInstPtr inst
, int stage_num
, int res_idx
,
119 int slot_num
, unsigned cmd
)
121 ScheduleEntry
* sched_entry
= inst
->resSched
.top();
123 if (!inst
->validMemAddr()) {
124 panic("Mem. Addr. must be set before requesting cache access\n");
127 MemCmd::Command pkt_cmd
;
129 switch (sched_entry
->cmd
)
132 pkt_cmd
= MemCmd::ReadReq
;
134 DPRINTF(InOrderCachePort
,
135 "[tid:%i]: Fetch request from [sn:%i] for addr %08p\n",
136 inst
->readTid(), inst
->seqNum
, inst
->getMemAddr());
140 panic("%i: Unexpected request type (%i) to %s", curTick(),
141 sched_entry
->cmd
, name());
144 return new CacheRequest(this, inst
, stage_num
, id
, slot_num
,
145 sched_entry
->cmd
, 0, pkt_cmd
,
146 0/*flags*/, this->cpu
->readCpuId(),
147 inst
->resSched
.top()->idx
);
151 FetchUnit::setupMemRequest(DynInstPtr inst
, CacheReqPtr cache_req
,
152 int acc_size
, int flags
)
154 ThreadID tid
= inst
->readTid();
155 Addr aligned_addr
= cacheBlockAlign(inst
->getMemAddr());
158 new Request(tid
, aligned_addr
, acc_size
, flags
,
159 inst
->instAddr(), cpu
->readCpuId(), tid
);
161 cache_req
->memReq
= inst
->fetchMemReq
;
164 std::list
<FetchUnit::FetchBlock
*>::iterator
165 FetchUnit::findBlock(std::list
<FetchBlock
*> &fetch_blocks
, int asid
,
168 std::list
<FetchBlock
*>::iterator fetch_it
= fetch_blocks
.begin();
169 std::list
<FetchBlock
*>::iterator end_it
= fetch_blocks
.end();
171 while (fetch_it
!= end_it
) {
172 if ((*fetch_it
)->asid
== asid
&&
173 (*fetch_it
)->addr
== block_addr
) {
183 std::list
<FetchUnit::FetchBlock
*>::iterator
184 FetchUnit::findReplacementBlock()
186 std::list
<FetchBlock
*>::iterator fetch_it
= fetchBuffer
.begin();
187 std::list
<FetchBlock
*>::iterator end_it
= fetchBuffer
.end();
189 while (fetch_it
!= end_it
) {
190 if ((*fetch_it
)->cnt
== 0) {
193 DPRINTF(InOrderCachePort
, "Block %08p has %i insts pending.\n",
194 (*fetch_it
)->addr
, (*fetch_it
)->cnt
);
203 FetchUnit::markBlockUsed(std::list
<FetchBlock
*>::iterator block_it
)
205 // Move block from whatever location it is in fetch buffer
206 // to the back (represents most-recently-used location)
207 if (block_it
!= fetchBuffer
.end()) {
208 FetchBlock
*mru_blk
= *block_it
;
209 fetchBuffer
.erase(block_it
);
210 fetchBuffer
.push_back(mru_blk
);
215 FetchUnit::execute(int slot_num
)
217 CacheReqPtr cache_req
= dynamic_cast<CacheReqPtr
>(reqMap
[slot_num
]);
220 if (cachePortBlocked
) {
221 DPRINTF(InOrderCachePort
, "Cache Port Blocked. Cannot Access\n");
222 cache_req
->setCompleted(false);
226 DynInstPtr inst
= cache_req
->inst
;
227 ThreadID tid
= inst
->readTid();
228 Addr block_addr
= cacheBlockAlign(inst
->getMemAddr());
229 int asid
= cpu
->asid
[tid
];
231 inst
->fault
= NoFault
;
233 switch (cache_req
->cmd
)
237 // Check to see if we've already got this request buffered
238 // or pending to be buffered
239 bool do_fetch
= true;
240 std::list
<FetchBlock
*>::iterator pending_it
;
241 pending_it
= findBlock(pendingFetch
, asid
, block_addr
);
242 if (pending_it
!= pendingFetch
.end()) {
243 (*pending_it
)->cnt
++;
246 DPRINTF(InOrderCachePort
, "%08p is a pending fetch block "
247 "(pending:%i).\n", block_addr
,
249 } else if (pendingFetch
.size() < fetchBuffSize
) {
250 std::list
<FetchBlock
*>::iterator buff_it
;
251 buff_it
= findBlock(fetchBuffer
, asid
, block_addr
);
252 if (buff_it
!= fetchBuffer
.end()) {
256 DPRINTF(InOrderCachePort
, "%08p is in fetch buffer"
257 "(pending:%i).\n", block_addr
, (*buff_it
)->cnt
);
262 DPRINTF(InOrderCachePort
, "Inst. [sn:%i] marked to be filled "
263 "through fetch buffer.\n", inst
->seqNum
);
264 cache_req
->fetchBufferFill
= true;
265 cache_req
->setCompleted(true);
269 // Check to see if there is room in the fetchbuffer for this instruction.
270 // If not, block this request.
271 if (pendingFetch
.size() >= fetchBuffSize
) {
272 DPRINTF(InOrderCachePort
, "No room available in fetch buffer.\n");
273 cache_req
->setCompleted(false);
277 doTLBAccess(inst
, cache_req
, cacheBlkSize
, 0, TheISA::TLB::Execute
);
279 if (inst
->fault
== NoFault
) {
280 DPRINTF(InOrderCachePort
,
281 "[tid:%u]: Initiating fetch access to %s for "
282 "addr:%#x (block:%#x)\n", tid
, name(),
283 cache_req
->inst
->getMemAddr(), block_addr
);
285 cache_req
->reqData
= new uint8_t[cacheBlkSize
];
287 inst
->setCurResSlot(slot_num
);
291 if (cache_req
->isMemAccPending()) {
292 pendingFetch
.push_back(new FetchBlock(asid
, block_addr
));
300 if (cache_req
->fetchBufferFill
) {
301 // Block request if it's depending on a previous fetch, but it hasnt made it yet
302 std::list
<FetchBlock
*>::iterator fetch_it
= findBlock(fetchBuffer
, asid
, block_addr
);
303 if (fetch_it
== fetchBuffer
.end()) {
304 DPRINTF(InOrderCachePort
, "%#x not available yet\n",
306 cache_req
->setCompleted(false);
310 // Make New Instruction
311 createMachInst(fetch_it
, inst
);
312 if (inst
->traceData
) {
313 inst
->traceData
->setStaticInst(inst
->staticInst
);
314 inst
->traceData
->setPC(inst
->pcState());
317 // FetchBuffer Book-Keeping
319 assert((*fetch_it
)->cnt
>= 0);
320 markBlockUsed(fetch_it
);
326 if (cache_req
->isMemAccComplete()) {
327 if (fetchBuffer
.size() >= fetchBuffSize
) {
328 // If there is no replacement block, then we'll just have
329 // to wait till that gets cleared before satisfying the fetch
330 // for this instruction
331 std::list
<FetchBlock
*>::iterator repl_it
=
332 findReplacementBlock();
333 if (repl_it
== fetchBuffer
.end()) {
334 DPRINTF(InOrderCachePort
, "Unable to find replacement block"
335 " and complete fetch.\n");
336 cache_req
->setCompleted(false);
340 fetchBuffer
.erase(repl_it
);
343 DPRINTF(InOrderCachePort
,
344 "[tid:%i]: Completing Fetch Access for [sn:%i]\n",
347 // Make New Instruction
348 std::list
<FetchBlock
*>::iterator fetch_it
=
349 findBlock(pendingFetch
, asid
, block_addr
);
351 assert(fetch_it
!= pendingFetch
.end());
352 assert((*fetch_it
)->valid
);
354 createMachInst(fetch_it
, inst
);
355 if (inst
->traceData
) {
356 inst
->traceData
->setStaticInst(inst
->staticInst
);
357 inst
->traceData
->setPC(inst
->pcState());
361 // Update instructions waiting on new fetch block
362 FetchBlock
*new_block
= (*fetch_it
);
364 assert(new_block
->cnt
>= 0);
366 // Finally, update FetchBuffer w/Pending Block into the
368 pendingFetch
.erase(fetch_it
);
369 fetchBuffer
.push_back(new_block
);
371 DPRINTF(InOrderCachePort
, "[tid:%i]: Instruction [sn:%i] is: %s\n",
373 inst
->staticInst
->disassemble(inst
->instAddr()));
375 inst
->unsetMemAddr();
377 delete cache_req
->dataPkt
;
381 DPRINTF(InOrderCachePort
,
382 "[tid:%i]: [sn:%i]: Unable to Complete Fetch Access\n",
384 DPRINTF(InOrderStall
,
385 "STALL: [tid:%i]: Fetch miss from %08p\n",
386 tid
, cache_req
->inst
->instAddr());
387 cache_req
->setCompleted(false);
388 // NOTE: For SwitchOnCacheMiss ThreadModel, we *don't* switch on
389 // fetch miss, but we could ...
390 // cache_req->setMemStall(true);
395 fatal("Unrecognized command to %s", resName
);
400 FetchUnit::processCacheCompletion(PacketPtr pkt
)
402 // Cast to correct packet type
403 CacheReqPacket
* cache_pkt
= dynamic_cast<CacheReqPacket
*>(pkt
);
406 if (cache_pkt
->cacheReq
->isSquashed()) {
407 DPRINTF(InOrderCachePort
,
408 "Ignoring completion of squashed access, [tid:%i] [sn:%i]\n",
409 cache_pkt
->cacheReq
->getInst()->readTid(),
410 cache_pkt
->cacheReq
->getInst()->seqNum
);
412 "Ignoring completion of squashed access, [tid:%i] [sn:%i]\n",
413 cache_pkt
->cacheReq
->getTid(),
414 cache_pkt
->cacheReq
->seqNum
);
416 cache_pkt
->cacheReq
->done();
423 Addr block_addr
= cacheBlockAlign(cache_pkt
->cacheReq
->
424 getInst()->getMemAddr());
426 DPRINTF(InOrderCachePort
,
427 "[tid:%u]: [sn:%i]: Waking from fetch access to addr:%#x(phys:%#x), size:%i\n",
428 cache_pkt
->cacheReq
->getInst()->readTid(),
429 cache_pkt
->cacheReq
->getInst()->seqNum
,
430 block_addr
, cache_pkt
->getAddr(), cache_pkt
->getSize());
432 // Cast to correct request type
433 CacheRequest
*cache_req
= dynamic_cast<CacheReqPtr
>(
434 findRequest(cache_pkt
->cacheReq
->getInst(), cache_pkt
->instIdx
));
437 panic("[tid:%u]: [sn:%i]: Can't find slot for fetch access to "
438 "addr. %08p\n", cache_pkt
->cacheReq
->getInst()->readTid(),
439 cache_pkt
->cacheReq
->getInst()->seqNum
,
443 // Get resource request info
444 unsigned stage_num
= cache_req
->getStageNum();
445 DynInstPtr inst
= cache_req
->inst
;
446 ThreadID tid
= cache_req
->inst
->readTid();
447 short asid
= cpu
->asid
[tid
];
449 assert(!cache_req
->isSquashed());
450 assert(inst
->resSched
.top()->cmd
== CompleteFetch
);
452 DPRINTF(InOrderCachePort
,
453 "[tid:%u]: [sn:%i]: Processing fetch access for block %#x\n",
454 tid
, inst
->seqNum
, block_addr
);
456 std::list
<FetchBlock
*>::iterator pend_it
= findBlock(pendingFetch
, asid
,
458 assert(pend_it
!= pendingFetch
.end());
460 // Copy Data to pendingFetch queue...
461 (*pend_it
)->block
= new uint8_t[cacheBlkSize
];
462 memcpy((*pend_it
)->block
, cache_pkt
->getPtr
<uint8_t>(), cacheBlkSize
);
463 (*pend_it
)->valid
= true;
465 cache_req
->setMemAccPending(false);
466 cache_req
->setMemAccCompleted();
468 if (cache_req
->isMemStall() &&
469 cpu
->threadModel
== InOrderCPU::SwitchOnCacheMiss
) {
470 DPRINTF(InOrderCachePort
, "[tid:%u] Waking up from Cache Miss.\n",
473 cpu
->activateContext(tid
);
475 DPRINTF(ThreadModel
, "Activating [tid:%i] after return from cache"
479 // Wake up the CPU (if it went to sleep and was waiting on this
480 // completion event).
483 DPRINTF(Activity
, "[tid:%u] Activating %s due to cache completion\n",
484 tid
, cpu
->pipelineStage
[stage_num
]->name());
486 cpu
->switchToActive(stage_num
);
490 FetchUnit::squashCacheRequest(CacheReqPtr req_ptr
)
492 DynInstPtr inst
= req_ptr
->getInst();
493 ThreadID tid
= inst
->readTid();
494 Addr block_addr
= cacheBlockAlign(inst
->getMemAddr());
495 int asid
= cpu
->asid
[tid
];
497 // Check Fetch Buffer (or pending fetch) for this block and
498 // update pending counts
499 std::list
<FetchBlock
*>::iterator buff_it
= findBlock(fetchBuffer
,
502 if (buff_it
!= fetchBuffer
.end()) {
504 DPRINTF(InOrderCachePort
, "[sn:%i] Removing Pending Fetch "
505 "for Buffer block %08p (cnt=%i)\n", inst
->seqNum
,
506 block_addr
, (*buff_it
)->cnt
);
508 std::list
<FetchBlock
*>::iterator block_it
= findBlock(pendingFetch
,
511 if (block_it
!= pendingFetch
.end()) {
513 if ((*block_it
)->cnt
== 0) {
514 DPRINTF(InOrderCachePort
, "[sn:%i] Removing Pending Fetch "
515 "for block %08p (cnt=%i)\n", inst
->seqNum
,
516 block_addr
, (*block_it
)->cnt
);
517 pendingFetch
.erase(block_it
);
522 CacheUnit::squashCacheRequest(req_ptr
);