src/cpu/inorder/resources/fetch_unit.cc

   1 /*
   2  * Copyright (c) 2011 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #include <vector>
  33 #include <list>
  34
  35 #include "arch/isa_traits.hh"
  36 #include "arch/locked_mem.hh"
  37 #include "arch/utility.hh"
  38 #include "arch/predecoder.hh"
  39 #include "config/the_isa.hh"
  40 #include "cpu/inorder/resources/cache_unit.hh"
  41 #include "cpu/inorder/resources/fetch_unit.hh"
  42 #include "cpu/inorder/pipeline_traits.hh"
  43 #include "cpu/inorder/cpu.hh"
  44 #include "cpu/inorder/resource_pool.hh"
  45 #include "mem/request.hh"
  46
  47 using namespace std;
  48 using namespace TheISA;
  49 using namespace ThePipeline;
  50
  51 FetchUnit::FetchUnit(string res_name, int res_id, int res_width,
  52                      int res_latency, InOrderCPU *_cpu,
  53                      ThePipeline::Params *params)
  54     : CacheUnit(res_name, res_id, res_width, res_latency, _cpu, params),
  55       instSize(sizeof(TheISA::MachInst)), fetchBuffSize(params->fetchBuffSize),
  56       predecoder(NULL)
  57 { }
  58
  59 void
  60 FetchUnit::createMachInst(std::list<FetchBlock*>::iterator fetch_it,
  61                           DynInstPtr inst)
  62 {
  63     ExtMachInst ext_inst;
  64     Addr block_addr = cacheBlockAlign(inst->getMemAddr());
  65     Addr fetch_addr = inst->getMemAddr();
  66     unsigned fetch_offset = (fetch_addr - block_addr) / instSize;
  67     ThreadID tid = inst->readTid();
  68     TheISA::PCState instPC = inst->pcState();
  69
  70
  71     DPRINTF(InOrderCachePort, "Creating instruction [sn:%i] w/fetch data @"
  72             "addr:%08p block:%08p\n", inst->seqNum, fetch_addr, block_addr);
  73
  74     assert((*fetch_it)->valid);
  75
  76     TheISA::MachInst *fetchInsts =
  77         reinterpret_cast<TheISA::MachInst *>((*fetch_it)->block);
  78
  79     MachInst mach_inst =
  80         TheISA::gtoh(fetchInsts[fetch_offset]);
  81
  82     predecoder.setTC(cpu->thread[tid]->getTC());
  83     predecoder.moreBytes(instPC, inst->instAddr(), mach_inst);
  84     ext_inst = predecoder.getExtMachInst(instPC);
  85
  86     inst->pcState(instPC);
  87     inst->setMachInst(ext_inst);
  88 }
  89
  90 int
  91 FetchUnit::getSlot(DynInstPtr inst)
  92 {
  93     if (tlbBlocked[inst->threadNumber]) {
  94         return -1;
  95     }
  96
  97     if (!inst->validMemAddr()) {
  98         panic("[tid:%i][sn:%i] Mem. Addr. must be set before requesting "
  99               "cache access\n", inst->readTid(), inst->seqNum);
 100     }
 101
 102     int new_slot = Resource::getSlot(inst);
 103
 104     if (new_slot == -1)
 105         return -1;
 106
 107     inst->memTime = curTick();
 108     return new_slot;
 109 }
 110
 111 void
 112 FetchUnit::removeAddrDependency(DynInstPtr inst)
 113 {
 114     inst->unsetMemAddr();
 115 }
 116
 117 ResReqPtr
 118 FetchUnit::getRequest(DynInstPtr inst, int stage_num, int res_idx,
 119                      int slot_num, unsigned cmd)
 120 {
 121     ScheduleEntry* sched_entry = *inst->curSkedEntry;
 122
 123     if (!inst->validMemAddr()) {
 124         panic("Mem. Addr. must be set before requesting cache access\n");
 125     }
 126
 127     MemCmd::Command pkt_cmd;
 128
 129     switch (sched_entry->cmd)
 130     {
 131       case InitiateFetch:
 132         pkt_cmd = MemCmd::ReadReq;
 133
 134         DPRINTF(InOrderCachePort,
 135                 "[tid:%i]: Fetch request from [sn:%i] for addr %08p\n",
 136                 inst->readTid(), inst->seqNum, inst->getMemAddr());
 137         break;
 138
 139       default:
 140         panic("%i: Unexpected request type (%i) to %s", curTick(),
 141               sched_entry->cmd, name());
 142     }
 143
 144     return new CacheRequest(this, inst, stage_num, id, slot_num,
 145                             sched_entry->cmd, 0, pkt_cmd,
 146                             0/*flags*/, this->cpu->readCpuId(),
 147                             inst->curSkedEntry->idx);
 148 }
 149
 150 void
 151 FetchUnit::setupMemRequest(DynInstPtr inst, CacheReqPtr cache_req,
 152                            int acc_size, int flags)
 153 {
 154     ThreadID tid = inst->readTid();
 155     Addr aligned_addr = cacheBlockAlign(inst->getMemAddr());
 156
 157     inst->fetchMemReq =
 158             new Request(tid, aligned_addr, acc_size, flags,
 159                         inst->instAddr(), cpu->readCpuId(), tid);
 160
 161     cache_req->memReq = inst->fetchMemReq;
 162 }
 163
 164 std::list<FetchUnit::FetchBlock*>::iterator
 165 FetchUnit::findBlock(std::list<FetchBlock*> &fetch_blocks, int asid,
 166                      Addr block_addr)
 167 {
 168     std::list<FetchBlock*>::iterator fetch_it = fetch_blocks.begin();
 169     std::list<FetchBlock*>::iterator end_it = fetch_blocks.end();
 170
 171     while (fetch_it != end_it) {
 172         if ((*fetch_it)->asid == asid &&
 173             (*fetch_it)->addr == block_addr) {
 174             return fetch_it;
 175         }
 176
 177         fetch_it++;
 178     }
 179
 180     return fetch_it;
 181 }
 182
 183 std::list<FetchUnit::FetchBlock*>::iterator
 184 FetchUnit::findReplacementBlock()
 185 {
 186     std::list<FetchBlock*>::iterator fetch_it = fetchBuffer.begin();
 187     std::list<FetchBlock*>::iterator end_it = fetchBuffer.end();
 188
 189     while (fetch_it != end_it) {
 190         if ((*fetch_it)->cnt == 0) {
 191             return fetch_it;
 192         } else {
 193             DPRINTF(InOrderCachePort, "Block %08p has %i insts pending.\n",
 194                     (*fetch_it)->addr, (*fetch_it)->cnt);
 195         }
 196         fetch_it++;
 197     }
 198
 199     return fetch_it;
 200 }
 201
 202 void
 203 FetchUnit::markBlockUsed(std::list<FetchBlock*>::iterator block_it)
 204 {
 205     // Move block from whatever location it is in fetch buffer
 206     // to the back (represents most-recently-used location)
 207     if (block_it != fetchBuffer.end()) {
 208         FetchBlock *mru_blk = *block_it;
 209         fetchBuffer.erase(block_it);
 210         fetchBuffer.push_back(mru_blk);
 211     }
 212 }
 213
 214 void
 215 FetchUnit::execute(int slot_num)
 216 {
 217     CacheReqPtr cache_req = dynamic_cast<CacheReqPtr>(reqMap[slot_num]);
 218     assert(cache_req);
 219
 220     if (cachePortBlocked) {
 221         DPRINTF(InOrderCachePort, "Cache Port Blocked. Cannot Access\n");
 222         cache_req->setCompleted(false);
 223         return;
 224     }
 225
 226     DynInstPtr inst = cache_req->inst;
 227     ThreadID tid = inst->readTid();
 228     Addr block_addr = cacheBlockAlign(inst->getMemAddr());
 229     int asid = cpu->asid[tid];
 230
 231     inst->fault = NoFault;
 232
 233     switch (cache_req->cmd)
 234     {
 235       case InitiateFetch:
 236         {
 237             // Check to see if we've already got this request buffered
 238             // or pending to be buffered
 239             bool do_fetch = true;
 240             std::list<FetchBlock*>::iterator pending_it;
 241             pending_it = findBlock(pendingFetch, asid, block_addr);
 242             if (pending_it != pendingFetch.end()) {
 243                 (*pending_it)->cnt++;
 244                 do_fetch = false;
 245
 246                 DPRINTF(InOrderCachePort, "%08p is a pending fetch block "
 247                         "(pending:%i).\n", block_addr,
 248                         (*pending_it)->cnt);
 249             } else if (pendingFetch.size() < fetchBuffSize) {
 250                 std::list<FetchBlock*>::iterator buff_it;
 251                 buff_it = findBlock(fetchBuffer, asid, block_addr);
 252                 if (buff_it  != fetchBuffer.end()) {
 253                     (*buff_it)->cnt++;
 254                     do_fetch = false;
 255
 256                     DPRINTF(InOrderCachePort, "%08p is in fetch buffer"
 257                             "(pending:%i).\n", block_addr, (*buff_it)->cnt);
 258                 }
 259             }
 260
 261             if (!do_fetch) {
 262                 DPRINTF(InOrderCachePort, "Inst. [sn:%i] marked to be filled "
 263                         "through fetch buffer.\n", inst->seqNum);
 264                 cache_req->fetchBufferFill = true;
 265                 cache_req->setCompleted(true);
 266                 return;
 267             }
 268
 269             // Check to see if there is room in the fetchbuffer for this instruction.
 270             // If not, block this request.
 271             if (pendingFetch.size() >= fetchBuffSize) {
 272                 DPRINTF(InOrderCachePort, "No room available in fetch buffer.\n");
 273                 cache_req->setCompleted(false);
 274                 return;
 275             }
 276
 277             doTLBAccess(inst, cache_req, cacheBlkSize, 0, TheISA::TLB::Execute);
 278
 279             if (inst->fault == NoFault) {
 280                 DPRINTF(InOrderCachePort,
 281                         "[tid:%u]: Initiating fetch access to %s for "
 282                         "addr:%#x (block:%#x)\n", tid, name(),
 283                         cache_req->inst->getMemAddr(), block_addr);
 284
 285                 cache_req->reqData = new uint8_t[cacheBlkSize];
 286
 287                 inst->setCurResSlot(slot_num);
 288
 289                 doCacheAccess(inst);
 290
 291                 if (cache_req->isMemAccPending()) {
 292                     pendingFetch.push_back(new FetchBlock(asid, block_addr));
 293                 }
 294             }
 295
 296             break;
 297         }
 298
 299       case CompleteFetch:
 300         if (cache_req->fetchBufferFill) {
 301             // Block request if it's depending on a previous fetch, but it hasnt made it yet
 302             std::list<FetchBlock*>::iterator fetch_it = findBlock(fetchBuffer, asid, block_addr);
 303             if (fetch_it == fetchBuffer.end()) {
 304                 DPRINTF(InOrderCachePort, "%#x not available yet\n",
 305                         block_addr);
 306                 cache_req->setCompleted(false);
 307                 return;
 308             }
 309
 310             // Make New Instruction
 311             createMachInst(fetch_it, inst);
 312             if (inst->traceData) {
 313                 inst->traceData->setStaticInst(inst->staticInst);
 314                 inst->traceData->setPC(inst->pcState());
 315             }
 316
 317             // FetchBuffer Book-Keeping
 318             (*fetch_it)->cnt--;
 319             assert((*fetch_it)->cnt >= 0);
 320             markBlockUsed(fetch_it);
 321
 322             cache_req->done();
 323             return;
 324         }
 325
 326         if (cache_req->isMemAccComplete()) {
 327             if (fetchBuffer.size() >= fetchBuffSize) {
 328                 // If there is no replacement block, then we'll just have
 329                 // to wait till that gets cleared before satisfying the fetch
 330                 // for this instruction
 331                 std::list<FetchBlock*>::iterator repl_it  =
 332                     findReplacementBlock();
 333                 if (repl_it == fetchBuffer.end()) {
 334                     DPRINTF(InOrderCachePort, "Unable to find replacement block"
 335                             " and complete fetch.\n");
 336                     cache_req->setCompleted(false);
 337                     return;
 338                 }
 339
 340                 fetchBuffer.erase(repl_it);
 341             }
 342
 343             DPRINTF(InOrderCachePort,
 344                     "[tid:%i]: Completing Fetch Access for [sn:%i]\n",
 345                     tid, inst->seqNum);
 346
 347             // Make New Instruction
 348             std::list<FetchBlock*>::iterator fetch_it  =
 349                 findBlock(pendingFetch, asid, block_addr);
 350
 351             assert(fetch_it != pendingFetch.end());
 352             assert((*fetch_it)->valid);
 353
 354             createMachInst(fetch_it, inst);
 355             if (inst->traceData) {
 356                 inst->traceData->setStaticInst(inst->staticInst);
 357                 inst->traceData->setPC(inst->pcState());
 358             }
 359
 360
 361             // Update instructions waiting on new fetch block
 362             FetchBlock *new_block = (*fetch_it);
 363             new_block->cnt--;
 364             assert(new_block->cnt >= 0);
 365
 366             // Finally, update FetchBuffer w/Pending Block into the
 367             // MRU location
 368             pendingFetch.erase(fetch_it);
 369             fetchBuffer.push_back(new_block);
 370
 371             DPRINTF(InOrderCachePort, "[tid:%i]: Instruction [sn:%i] is: %s\n",
 372                     tid, inst->seqNum,
 373                     inst->staticInst->disassemble(inst->instAddr()));
 374
 375             inst->unsetMemAddr();
 376
 377             delete cache_req->dataPkt;
 378
 379             cache_req->done();
 380         } else {
 381             DPRINTF(InOrderCachePort,
 382                      "[tid:%i]: [sn:%i]: Unable to Complete Fetch Access\n",
 383                     tid, inst->seqNum);
 384             DPRINTF(InOrderStall,
 385                     "STALL: [tid:%i]: Fetch miss from %08p\n",
 386                     tid, cache_req->inst->instAddr());
 387             cache_req->setCompleted(false);
 388             // NOTE: For SwitchOnCacheMiss ThreadModel, we *don't* switch on
 389             //       fetch miss, but we could ...
 390             // cache_req->setMemStall(true);
 391         }
 392         break;
 393
 394       default:
 395         fatal("Unrecognized command to %s", resName);
 396     }
 397 }
 398
 399 void
 400 FetchUnit::processCacheCompletion(PacketPtr pkt)
 401 {
 402     // Cast to correct packet type
 403     CacheReqPacket* cache_pkt = dynamic_cast<CacheReqPacket*>(pkt);
 404     assert(cache_pkt);
 405
 406     if (cache_pkt->cacheReq->isSquashed()) {
 407         DPRINTF(InOrderCachePort,
 408                 "Ignoring completion of squashed access, [tid:%i] [sn:%i]\n",
 409                 cache_pkt->cacheReq->getInst()->readTid(),
 410                 cache_pkt->cacheReq->getInst()->seqNum);
 411         DPRINTF(RefCount,
 412                 "Ignoring completion of squashed access, [tid:%i] [sn:%i]\n",
 413                 cache_pkt->cacheReq->getTid(),
 414                 cache_pkt->cacheReq->seqNum);
 415
 416         cache_pkt->cacheReq->done();
 417         delete cache_pkt;
 418
 419         cpu->wakeCPU();
 420         return;
 421     }
 422
 423     Addr block_addr = cacheBlockAlign(cache_pkt->cacheReq->
 424                                       getInst()->getMemAddr());
 425
 426     DPRINTF(InOrderCachePort,
 427             "[tid:%u]: [sn:%i]: Waking from fetch access to addr:%#x(phys:%#x), size:%i\n",
 428             cache_pkt->cacheReq->getInst()->readTid(),
 429             cache_pkt->cacheReq->getInst()->seqNum,
 430             block_addr, cache_pkt->getAddr(), cache_pkt->getSize());
 431
 432     // Cast to correct request type
 433     CacheRequest *cache_req = dynamic_cast<CacheReqPtr>(
 434         findRequest(cache_pkt->cacheReq->getInst(), cache_pkt->instIdx));
 435
 436     if (!cache_req) {
 437         panic("[tid:%u]: [sn:%i]: Can't find slot for fetch access to "
 438               "addr. %08p\n", cache_pkt->cacheReq->getInst()->readTid(),
 439               cache_pkt->cacheReq->getInst()->seqNum,
 440               block_addr);
 441     }
 442
 443     // Get resource request info
 444     unsigned stage_num = cache_req->getStageNum();
 445     DynInstPtr inst = cache_req->inst;
 446     ThreadID tid = cache_req->inst->readTid();
 447     short asid = cpu->asid[tid];
 448
 449     assert(!cache_req->isSquashed());
 450     assert(inst->curSkedEntry->cmd == CompleteFetch);
 451
 452     DPRINTF(InOrderCachePort,
 453             "[tid:%u]: [sn:%i]: Processing fetch access for block %#x\n",
 454             tid, inst->seqNum, block_addr);
 455
 456     std::list<FetchBlock*>::iterator pend_it = findBlock(pendingFetch, asid,
 457                                                          block_addr);
 458     assert(pend_it != pendingFetch.end());
 459
 460     // Copy Data to pendingFetch queue...
 461     (*pend_it)->block = new uint8_t[cacheBlkSize];
 462     memcpy((*pend_it)->block, cache_pkt->getPtr<uint8_t>(), cacheBlkSize);
 463     (*pend_it)->valid = true;
 464
 465     cache_req->setMemAccPending(false);
 466     cache_req->setMemAccCompleted();
 467
 468     if (cache_req->isMemStall() &&
 469         cpu->threadModel == InOrderCPU::SwitchOnCacheMiss) {
 470         DPRINTF(InOrderCachePort, "[tid:%u] Waking up from Cache Miss.\n",
 471                 tid);
 472
 473         cpu->activateContext(tid);
 474
 475         DPRINTF(ThreadModel, "Activating [tid:%i] after return from cache"
 476                 "miss.\n", tid);
 477     }
 478
 479     // Wake up the CPU (if it went to sleep and was waiting on this
 480     // completion event).
 481     cpu->wakeCPU();
 482
 483     DPRINTF(Activity, "[tid:%u] Activating %s due to cache completion\n",
 484             tid, cpu->pipelineStage[stage_num]->name());
 485
 486     cpu->switchToActive(stage_num);
 487 }
 488
 489 void
 490 FetchUnit::squashCacheRequest(CacheReqPtr req_ptr)
 491 {
 492     DynInstPtr inst = req_ptr->getInst();
 493     ThreadID tid = inst->readTid();
 494     Addr block_addr = cacheBlockAlign(inst->getMemAddr());
 495     int asid = cpu->asid[tid];
 496
 497     // Check Fetch Buffer (or pending fetch) for this block and
 498     // update pending counts
 499     std::list<FetchBlock*>::iterator buff_it = findBlock(fetchBuffer,
 500                                                          asid,
 501                                                          block_addr);
 502     if (buff_it != fetchBuffer.end()) {
 503         (*buff_it)->cnt--;
 504         DPRINTF(InOrderCachePort, "[sn:%i] Removing Pending Fetch "
 505                 "for Buffer block %08p (cnt=%i)\n", inst->seqNum,
 506                 block_addr, (*buff_it)->cnt);
 507     } else {
 508         std::list<FetchBlock*>::iterator block_it = findBlock(pendingFetch,
 509                                                               asid,
 510                                                               block_addr);
 511         if (block_it != pendingFetch.end()) {
 512             (*block_it)->cnt--;
 513             if ((*block_it)->cnt == 0) {
 514                 DPRINTF(InOrderCachePort, "[sn:%i] Removing Pending Fetch "
 515                         "for block %08p (cnt=%i)\n", inst->seqNum,
 516                         block_addr, (*block_it)->cnt);
 517                 pendingFetch.erase(block_it);
 518             }
 519         }
 520     }
 521
 522     CacheUnit::squashCacheRequest(req_ptr);
 523 }
 524