src/cpu/inorder/resources/fetch_unit.cc

   1 /*
   2  * Copyright (c) 2011 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #include <list>
  33 #include <vector>
  34
  35 #include "arch/isa_traits.hh"
  36 #include "arch/locked_mem.hh"
  37 #include "arch/predecoder.hh"
  38 #include "arch/utility.hh"
  39 #include "config/the_isa.hh"
  40 #include "cpu/inorder/resources/cache_unit.hh"
  41 #include "cpu/inorder/resources/fetch_unit.hh"
  42 #include "cpu/inorder/cpu.hh"
  43 #include "cpu/inorder/pipeline_traits.hh"
  44 #include "cpu/inorder/resource_pool.hh"
  45 #include "debug/Activity.hh"
  46 #include "debug/InOrderCachePort.hh"
  47 #include "debug/InOrderStall.hh"
  48 #include "debug/RefCount.hh"
  49 #include "debug/ThreadModel.hh"
  50 #include "mem/request.hh"
  51
  52 using namespace std;
  53 using namespace TheISA;
  54 using namespace ThePipeline;
  55
  56 FetchUnit::FetchUnit(string res_name, int res_id, int res_width,
  57                      int res_latency, InOrderCPU *_cpu,
  58                      ThePipeline::Params *params)
  59     : CacheUnit(res_name, res_id, res_width, res_latency, _cpu, params),
  60       instSize(sizeof(TheISA::MachInst)), fetchBuffSize(params->fetchBuffSize),
  61       predecoder(NULL)
  62 { }
  63
  64 FetchUnit::~FetchUnit()
  65 {
  66     std::list<FetchBlock*>::iterator fetch_it = fetchBuffer.begin();
  67     std::list<FetchBlock*>::iterator end_it = fetchBuffer.end();
  68     while (fetch_it != end_it) {
  69         delete (*fetch_it)->block;
  70         delete *fetch_it;
  71         fetch_it++;
  72     }
  73     fetchBuffer.clear();
  74
  75
  76     std::list<FetchBlock*>::iterator pend_it = pendingFetch.begin();
  77     std::list<FetchBlock*>::iterator pend_end = pendingFetch.end();
  78     while (pend_it != pend_end) {
  79         if ((*pend_it)->block) {
  80             delete (*pend_it)->block;
  81         }
  82
  83         delete *pend_it;
  84         pend_it++;
  85     }
  86     pendingFetch.clear();
  87 }
  88
  89 void
  90 FetchUnit::createMachInst(std::list<FetchBlock*>::iterator fetch_it,
  91                           DynInstPtr inst)
  92 {
  93     ExtMachInst ext_inst;
  94     Addr block_addr = cacheBlockAlign(inst->getMemAddr());
  95     Addr fetch_addr = inst->getMemAddr();
  96     unsigned fetch_offset = (fetch_addr - block_addr) / instSize;
  97     ThreadID tid = inst->readTid();
  98     TheISA::PCState instPC = inst->pcState();
  99
 100
 101     DPRINTF(InOrderCachePort, "Creating instruction [sn:%i] w/fetch data @"
 102             "addr:%08p block:%08p\n", inst->seqNum, fetch_addr, block_addr);
 103
 104     assert((*fetch_it)->valid);
 105
 106     TheISA::MachInst *fetchInsts =
 107         reinterpret_cast<TheISA::MachInst *>((*fetch_it)->block);
 108
 109     MachInst mach_inst =
 110         TheISA::gtoh(fetchInsts[fetch_offset]);
 111
 112     predecoder.setTC(cpu->thread[tid]->getTC());
 113     predecoder.moreBytes(instPC, inst->instAddr(), mach_inst);
 114     ext_inst = predecoder.getExtMachInst(instPC);
 115
 116     inst->pcState(instPC);
 117     inst->setMachInst(ext_inst);
 118 }
 119
 120 int
 121 FetchUnit::getSlot(DynInstPtr inst)
 122 {
 123     if (tlbBlocked[inst->threadNumber]) {
 124         return -1;
 125     }
 126
 127     if (!inst->validMemAddr()) {
 128         panic("[tid:%i][sn:%i] Mem. Addr. must be set before requesting "
 129               "cache access\n", inst->readTid(), inst->seqNum);
 130     }
 131
 132     int new_slot = Resource::getSlot(inst);
 133
 134     if (new_slot == -1)
 135         return -1;
 136
 137     inst->memTime = curTick();
 138     return new_slot;
 139 }
 140
 141 void
 142 FetchUnit::removeAddrDependency(DynInstPtr inst)
 143 {
 144     inst->unsetMemAddr();
 145 }
 146
 147 ResReqPtr
 148 FetchUnit::getRequest(DynInstPtr inst, int stage_num, int res_idx,
 149                      int slot_num, unsigned cmd)
 150 {
 151     ScheduleEntry* sched_entry = *inst->curSkedEntry;
 152     CacheRequest* cache_req = dynamic_cast<CacheRequest*>(reqs[slot_num]);
 153
 154     if (!inst->validMemAddr()) {
 155         panic("Mem. Addr. must be set before requesting cache access\n");
 156     }
 157
 158     assert(sched_entry->cmd == InitiateFetch);
 159
 160     DPRINTF(InOrderCachePort,
 161             "[tid:%i]: Fetch request from [sn:%i] for addr %08p\n",
 162             inst->readTid(), inst->seqNum, inst->getMemAddr());
 163
 164     cache_req->setRequest(inst, stage_num, id, slot_num,
 165                           sched_entry->cmd, MemCmd::ReadReq,
 166                           inst->curSkedEntry->idx);
 167
 168     return cache_req;
 169 }
 170
 171 void
 172 FetchUnit::setupMemRequest(DynInstPtr inst, CacheReqPtr cache_req,
 173                            int acc_size, int flags)
 174 {
 175     ThreadID tid = inst->readTid();
 176     Addr aligned_addr = cacheBlockAlign(inst->getMemAddr());
 177
 178     if (inst->fetchMemReq == NULL)
 179         inst->fetchMemReq =
 180             new Request(tid, aligned_addr, acc_size, flags,
 181                         inst->instAddr(), cpu->readCpuId(), tid);
 182
 183
 184     cache_req->memReq = inst->fetchMemReq;
 185 }
 186
 187 std::list<FetchUnit::FetchBlock*>::iterator
 188 FetchUnit::findBlock(std::list<FetchBlock*> &fetch_blocks, int asid,
 189                      Addr block_addr)
 190 {
 191     std::list<FetchBlock*>::iterator fetch_it = fetch_blocks.begin();
 192     std::list<FetchBlock*>::iterator end_it = fetch_blocks.end();
 193
 194     while (fetch_it != end_it) {
 195         if ((*fetch_it)->asid == asid &&
 196             (*fetch_it)->addr == block_addr) {
 197             return fetch_it;
 198         }
 199
 200         fetch_it++;
 201     }
 202
 203     return fetch_it;
 204 }
 205
 206 std::list<FetchUnit::FetchBlock*>::iterator
 207 FetchUnit::findReplacementBlock()
 208 {
 209     std::list<FetchBlock*>::iterator fetch_it = fetchBuffer.begin();
 210     std::list<FetchBlock*>::iterator end_it = fetchBuffer.end();
 211
 212     while (fetch_it != end_it) {
 213         if ((*fetch_it)->cnt == 0) {
 214             return fetch_it;
 215         } else {
 216             DPRINTF(InOrderCachePort, "Block %08p has %i insts pending.\n",
 217                     (*fetch_it)->addr, (*fetch_it)->cnt);
 218         }
 219         fetch_it++;
 220     }
 221
 222     return fetch_it;
 223 }
 224
 225 void
 226 FetchUnit::markBlockUsed(std::list<FetchBlock*>::iterator block_it)
 227 {
 228     // Move block from whatever location it is in fetch buffer
 229     // to the back (represents most-recently-used location)
 230     if (block_it != fetchBuffer.end()) {
 231         FetchBlock *mru_blk = *block_it;
 232         fetchBuffer.erase(block_it);
 233         fetchBuffer.push_back(mru_blk);
 234     }
 235 }
 236
 237 void
 238 FetchUnit::execute(int slot_num)
 239 {
 240     CacheReqPtr cache_req = dynamic_cast<CacheReqPtr>(reqs[slot_num]);
 241     assert(cache_req);
 242
 243     if (cachePortBlocked && cache_req->cmd == InitiateFetch) {
 244         DPRINTF(InOrderCachePort, "Cache Port Blocked. Cannot Access\n");
 245         cache_req->done(false);
 246         return;
 247     }
 248
 249     DynInstPtr inst = cache_req->inst;
 250     ThreadID tid = inst->readTid();
 251     Addr block_addr = cacheBlockAlign(inst->getMemAddr());
 252     int asid = cpu->asid[tid];
 253
 254     inst->fault = NoFault;
 255
 256     switch (cache_req->cmd)
 257     {
 258       case InitiateFetch:
 259         {
 260             // Check to see if we've already got this request buffered
 261             // or pending to be buffered
 262             bool do_fetch = true;
 263             std::list<FetchBlock*>::iterator pending_it;
 264             pending_it = findBlock(pendingFetch, asid, block_addr);
 265             if (pending_it != pendingFetch.end()) {
 266                 (*pending_it)->cnt++;
 267                 do_fetch = false;
 268
 269                 DPRINTF(InOrderCachePort, "%08p is a pending fetch block "
 270                         "(pending:%i).\n", block_addr,
 271                         (*pending_it)->cnt);
 272             } else if (pendingFetch.size() < fetchBuffSize) {
 273                 std::list<FetchBlock*>::iterator buff_it;
 274                 buff_it = findBlock(fetchBuffer, asid, block_addr);
 275                 if (buff_it  != fetchBuffer.end()) {
 276                     (*buff_it)->cnt++;
 277                     do_fetch = false;
 278
 279                     DPRINTF(InOrderCachePort, "%08p is in fetch buffer"
 280                             "(pending:%i).\n", block_addr, (*buff_it)->cnt);
 281                 }
 282             }
 283
 284             if (!do_fetch) {
 285                 DPRINTF(InOrderCachePort, "Inst. [sn:%i] marked to be filled "
 286                         "through fetch buffer.\n", inst->seqNum);
 287                 cache_req->fetchBufferFill = true;
 288                 cache_req->setCompleted(true);
 289                 return;
 290             }
 291
 292             // Check to see if there is room in the fetchbuffer for this instruction.
 293             // If not, block this request.
 294             if (pendingFetch.size() >= fetchBuffSize) {
 295                 DPRINTF(InOrderCachePort, "No room available in fetch buffer.\n");
 296                 cache_req->done();
 297                 return;
 298             }
 299
 300             doTLBAccess(inst, cache_req, cacheBlkSize, 0, TheISA::TLB::Execute);
 301
 302             if (inst->fault == NoFault) {
 303                 DPRINTF(InOrderCachePort,
 304                         "[tid:%u]: Initiating fetch access to %s for "
 305                         "addr:%#x (block:%#x)\n", tid, name(),
 306                         cache_req->inst->getMemAddr(), block_addr);
 307
 308                 cache_req->reqData = new uint8_t[cacheBlkSize];
 309
 310                 inst->setCurResSlot(slot_num);
 311
 312                 doCacheAccess(inst);
 313
 314                 if (cache_req->isMemAccPending()) {
 315                     pendingFetch.push_back(new FetchBlock(asid, block_addr));
 316                 }
 317             }
 318
 319             break;
 320         }
 321
 322       case CompleteFetch:
 323         if (cache_req->fetchBufferFill) {
 324             // Block request if it's depending on a previous fetch, but it hasnt made it yet
 325             std::list<FetchBlock*>::iterator fetch_it = findBlock(fetchBuffer, asid, block_addr);
 326             if (fetch_it == fetchBuffer.end()) {
 327                 DPRINTF(InOrderCachePort, "%#x not available yet\n",
 328                         block_addr);
 329                 cache_req->setCompleted(false);
 330                 return;
 331             }
 332
 333             // Make New Instruction
 334             createMachInst(fetch_it, inst);
 335             if (inst->traceData) {
 336                 inst->traceData->setStaticInst(inst->staticInst);
 337                 inst->traceData->setPC(inst->pcState());
 338             }
 339
 340             // FetchBuffer Book-Keeping
 341             (*fetch_it)->cnt--;
 342             assert((*fetch_it)->cnt >= 0);
 343             markBlockUsed(fetch_it);
 344
 345             cache_req->done();
 346             return;
 347         }
 348
 349         if (cache_req->isMemAccComplete()) {
 350             if (fetchBuffer.size() >= fetchBuffSize) {
 351                 // If there is no replacement block, then we'll just have
 352                 // to wait till that gets cleared before satisfying the fetch
 353                 // for this instruction
 354                 std::list<FetchBlock*>::iterator repl_it  =
 355                     findReplacementBlock();
 356                 if (repl_it == fetchBuffer.end()) {
 357                     DPRINTF(InOrderCachePort, "Unable to find replacement block"
 358                             " and complete fetch.\n");
 359                     cache_req->setCompleted(false);
 360                     return;
 361                 }
 362
 363                 delete [] (*repl_it)->block;
 364                 delete *repl_it;
 365                 fetchBuffer.erase(repl_it);
 366             }
 367
 368             DPRINTF(InOrderCachePort,
 369                     "[tid:%i]: Completing Fetch Access for [sn:%i]\n",
 370                     tid, inst->seqNum);
 371
 372             // Make New Instruction
 373             std::list<FetchBlock*>::iterator fetch_it  =
 374                 findBlock(pendingFetch, asid, block_addr);
 375
 376             assert(fetch_it != pendingFetch.end());
 377             assert((*fetch_it)->valid);
 378
 379             createMachInst(fetch_it, inst);
 380             if (inst->traceData) {
 381                 inst->traceData->setStaticInst(inst->staticInst);
 382                 inst->traceData->setPC(inst->pcState());
 383             }
 384
 385
 386             // Update instructions waiting on new fetch block
 387             FetchBlock *new_block = (*fetch_it);
 388             new_block->cnt--;
 389             assert(new_block->cnt >= 0);
 390
 391             // Finally, update FetchBuffer w/Pending Block into the
 392             // MRU location
 393             pendingFetch.erase(fetch_it);
 394             fetchBuffer.push_back(new_block);
 395
 396             DPRINTF(InOrderCachePort, "[tid:%i]: Instruction [sn:%i] is: %s\n",
 397                     tid, inst->seqNum,
 398                     inst->staticInst->disassemble(inst->instAddr()));
 399
 400             inst->unsetMemAddr();
 401
 402             delete cache_req->dataPkt;
 403
 404             cache_req->done();
 405         } else {
 406             DPRINTF(InOrderCachePort,
 407                      "[tid:%i]: [sn:%i]: Unable to Complete Fetch Access\n",
 408                     tid, inst->seqNum);
 409             DPRINTF(InOrderStall,
 410                     "STALL: [tid:%i]: Fetch miss from %08p\n",
 411                     tid, cache_req->inst->instAddr());
 412             cache_req->setCompleted(false);
 413             // NOTE: For SwitchOnCacheMiss ThreadModel, we *don't* switch on
 414             //       fetch miss, but we could ...
 415             // cache_req->setMemStall(true);
 416         }
 417         break;
 418
 419       default:
 420         fatal("Unrecognized command to %s", resName);
 421     }
 422 }
 423
 424 void
 425 FetchUnit::processCacheCompletion(PacketPtr pkt)
 426 {
 427     // Cast to correct packet type
 428     CacheReqPacket* cache_pkt = dynamic_cast<CacheReqPacket*>(pkt);
 429     assert(cache_pkt);
 430
 431     if (cache_pkt->cacheReq->isSquashed()) {
 432         DPRINTF(InOrderCachePort,
 433                 "Ignoring completion of squashed access, [tid:%i] [sn:%i]\n",
 434                 cache_pkt->cacheReq->getInst()->readTid(),
 435                 cache_pkt->cacheReq->getInst()->seqNum);
 436         DPRINTF(RefCount,
 437                 "Ignoring completion of squashed access, [tid:%i] [sn:%i]\n",
 438                 cache_pkt->cacheReq->getTid(),
 439                 cache_pkt->cacheReq->seqNum);
 440
 441         cache_pkt->cacheReq->done();
 442         cache_pkt->cacheReq->freeSlot();
 443         delete cache_pkt;
 444
 445         cpu->wakeCPU();
 446         return;
 447     }
 448
 449     Addr block_addr = cacheBlockAlign(cache_pkt->cacheReq->
 450                                       getInst()->getMemAddr());
 451
 452     DPRINTF(InOrderCachePort,
 453             "[tid:%u]: [sn:%i]: Waking from fetch access to addr:%#x(phys:%#x), size:%i\n",
 454             cache_pkt->cacheReq->getInst()->readTid(),
 455             cache_pkt->cacheReq->getInst()->seqNum,
 456             block_addr, cache_pkt->getAddr(), cache_pkt->getSize());
 457
 458     // Cast to correct request type
 459     CacheRequest *cache_req = dynamic_cast<CacheReqPtr>(
 460         findRequest(cache_pkt->cacheReq->getInst(), cache_pkt->instIdx));
 461
 462     if (!cache_req) {
 463         panic("[tid:%u]: [sn:%i]: Can't find slot for fetch access to "
 464               "addr. %08p\n", cache_pkt->cacheReq->getInst()->readTid(),
 465               cache_pkt->cacheReq->getInst()->seqNum,
 466               block_addr);
 467     }
 468
 469     // Get resource request info
 470     unsigned stage_num = cache_req->getStageNum();
 471     DynInstPtr inst = cache_req->inst;
 472     ThreadID tid = cache_req->inst->readTid();
 473     short asid = cpu->asid[tid];
 474
 475     assert(!cache_req->isSquashed());
 476     assert(inst->curSkedEntry->cmd == CompleteFetch);
 477
 478     DPRINTF(InOrderCachePort,
 479             "[tid:%u]: [sn:%i]: Processing fetch access for block %#x\n",
 480             tid, inst->seqNum, block_addr);
 481
 482     std::list<FetchBlock*>::iterator pend_it = findBlock(pendingFetch, asid,
 483                                                          block_addr);
 484     assert(pend_it != pendingFetch.end());
 485
 486     // Copy Data to pendingFetch queue...
 487     (*pend_it)->block = new uint8_t[cacheBlkSize];
 488     memcpy((*pend_it)->block, cache_pkt->getPtr<uint8_t>(), cacheBlkSize);
 489     (*pend_it)->valid = true;
 490
 491     cache_req->setMemAccPending(false);
 492     cache_req->setMemAccCompleted();
 493
 494     if (cache_req->isMemStall() &&
 495         cpu->threadModel == InOrderCPU::SwitchOnCacheMiss) {
 496         DPRINTF(InOrderCachePort, "[tid:%u] Waking up from Cache Miss.\n",
 497                 tid);
 498
 499         cpu->activateContext(tid);
 500
 501         DPRINTF(ThreadModel, "Activating [tid:%i] after return from cache"
 502                 "miss.\n", tid);
 503     }
 504
 505     // Wake up the CPU (if it went to sleep and was waiting on this
 506     // completion event).
 507     cpu->wakeCPU();
 508
 509     DPRINTF(Activity, "[tid:%u] Activating %s due to cache completion\n",
 510             tid, cpu->pipelineStage[stage_num]->name());
 511
 512     cpu->switchToActive(stage_num);
 513 }
 514
 515 void
 516 FetchUnit::squashCacheRequest(CacheReqPtr req_ptr)
 517 {
 518     DynInstPtr inst = req_ptr->getInst();
 519     ThreadID tid = inst->readTid();
 520     Addr block_addr = cacheBlockAlign(inst->getMemAddr());
 521     int asid = cpu->asid[tid];
 522
 523     // Check Fetch Buffer (or pending fetch) for this block and
 524     // update pending counts
 525     std::list<FetchBlock*>::iterator buff_it = findBlock(fetchBuffer,
 526                                                          asid,
 527                                                          block_addr);
 528     if (buff_it != fetchBuffer.end()) {
 529         (*buff_it)->cnt--;
 530         DPRINTF(InOrderCachePort, "[sn:%i] Removing Pending Fetch "
 531                 "for Buffer block %08p (cnt=%i)\n", inst->seqNum,
 532                 block_addr, (*buff_it)->cnt);
 533     } else {
 534         std::list<FetchBlock*>::iterator block_it = findBlock(pendingFetch,
 535                                                               asid,
 536                                                               block_addr);
 537         if (block_it != pendingFetch.end()) {
 538             (*block_it)->cnt--;
 539             if ((*block_it)->cnt == 0) {
 540                 DPRINTF(InOrderCachePort, "[sn:%i] Removing Pending Fetch "
 541                         "for block %08p (cnt=%i)\n", inst->seqNum,
 542                         block_addr, (*block_it)->cnt);
 543                 if ((*block_it)->block) {
 544                     delete [] (*block_it)->block;
 545                 }
 546                 delete *block_it;
 547                 pendingFetch.erase(block_it);
 548             }
 549         }
 550     }
 551
 552     CacheUnit::squashCacheRequest(req_ptr);
 553 }
 554