src/cpu/inorder/resources/fetch_unit.hh

   1 /*
   2  * Copyright (c) 2011 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #ifndef __CPU_INORDER_FETCH_UNIT_HH__
  33 #define __CPU_INORDER_FETCH_UNIT_HH__
  34
  35 #include <vector>
  36 #include <list>
  37 #include <string>
  38
  39 #include "arch/predecoder.hh"
  40 #include "arch/tlb.hh"
  41 #include "config/the_isa.hh"
  42 #include "cpu/inorder/inorder_dyn_inst.hh"
  43 #include "cpu/inorder/pipeline_traits.hh"
  44 #include "cpu/inorder/resource.hh"
  45 #include "cpu/inorder/resources/cache_unit.hh"
  46 #include "mem/packet.hh"
  47 #include "mem/packet_access.hh"
  48 #include "mem/port.hh"
  49 #include "params/InOrderCPU.hh"
  50 #include "sim/sim_object.hh"
  51
  52 class FetchUnit : public CacheUnit
  53 {
  54   public:
  55     typedef ThePipeline::DynInstPtr DynInstPtr;
  56
  57   public:
  58     FetchUnit(std::string res_name, int res_id, int res_width,
  59               int res_latency, InOrderCPU *_cpu, ThePipeline::Params *params);
  60
  61     /** Actions that this resources can take on an instruction */
  62     enum Command {
  63         InitiateFetch,
  64         CompleteFetch
  65     };
  66
  67   public:
  68     ResourceRequest* getRequest(DynInstPtr _inst, int stage_num,
  69                                 int res_idx, int slot_num,
  70                                 unsigned cmd);
  71
  72     int getSlot(DynInstPtr inst);
  73
  74     /** Executes one of the commands from the "Command" enum */
  75     void execute(int slot_num);
  76
  77     void squash(DynInstPtr inst, int stage_num,
  78                 InstSeqNum squash_seq_num, ThreadID tid);
  79
  80     /** After memory request is completed, then turn the fetched data
  81         into an instruction.
  82     */
  83     void processCacheCompletion(PacketPtr pkt);
  84
  85     /** Create request that will interface w/TLB and Memory objects */
  86     virtual void setupMemRequest(DynInstPtr inst, CacheReqPtr cache_req,
  87                                  int acc_size, int flags);
  88
  89     /** Align a PC to the start of an I-cache block. */
  90     Addr cacheBlockAlignPC(Addr addr)
  91     {
  92         return (addr & ~(cacheBlkMask));
  93     }
  94
  95     void removeAddrDependency(DynInstPtr inst);
  96
  97   public:
  98     /** The mem line being fetched. */
  99     uint8_t *fetchData[ThePipeline::MaxThreads];
 100
 101
 102     /** The Addr of the cacheline that has been loaded. */
 103     //Addr cacheBlockAddr[ThePipeline::MaxThreads];
 104     //unsigned fetchOffset[ThePipeline::MaxThreads];
 105 };
 106
 107 #endif //__CPU_FETCH_UNIT_HH__