src/cpu/inorder/resources/fetch_unit.hh

   1 /*
   2  * Copyright (c) 2011 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #ifndef __CPU_INORDER_FETCH_UNIT_HH__
  33 #define __CPU_INORDER_FETCH_UNIT_HH__
  34
  35 #include <list>
  36 #include <string>
  37 #include <vector>
  38
  39 #include "arch/predecoder.hh"
  40 #include "arch/tlb.hh"
  41 #include "config/the_isa.hh"
  42 #include "cpu/decode.hh"
  43 #include "cpu/inorder/resources/cache_unit.hh"
  44 #include "cpu/inorder/inorder_dyn_inst.hh"
  45 #include "cpu/inorder/pipeline_traits.hh"
  46 #include "cpu/inorder/resource.hh"
  47 #include "mem/packet.hh"
  48 #include "mem/packet_access.hh"
  49 #include "mem/port.hh"
  50 #include "params/InOrderCPU.hh"
  51 #include "sim/sim_object.hh"
  52
  53 class FetchUnit : public CacheUnit
  54 {
  55   public:
  56     FetchUnit(std::string res_name, int res_id, int res_width,
  57               int res_latency, InOrderCPU *_cpu, ThePipeline::Params *params);
  58
  59     virtual ~FetchUnit();
  60
  61     typedef ThePipeline::DynInstPtr DynInstPtr;
  62     typedef TheISA::ExtMachInst ExtMachInst;
  63
  64     struct FetchBlock {
  65         int asid;
  66         Addr addr;
  67         uint8_t *block;
  68         short cnt;
  69         bool valid;
  70
  71         FetchBlock(int _asid, Addr _addr)
  72             : asid(_asid), addr(_addr), block(NULL), cnt(1), valid(false)
  73         { }
  74     };
  75
  76     /** Actions that this resource can take on an instruction */
  77     enum Command {
  78         InitiateFetch,
  79         CompleteFetch
  80     };
  81
  82
  83     ResourceRequest* getRequest(DynInstPtr _inst, int stage_num,
  84                                 int res_idx, int slot_num,
  85                                 unsigned cmd);
  86
  87     /** Executes one of the commands from the "Command" enum */
  88     void execute(int slot_num);
  89
  90     void trap(Fault fault, ThreadID tid, DynInstPtr inst);
  91
  92     Decoder decoder;
  93
  94   private:
  95     void squashCacheRequest(CacheReqPtr req_ptr);
  96
  97     void createMachInst(std::list<FetchBlock*>::iterator fetch_it,
  98                         DynInstPtr inst);
  99
 100     /** After memory request is completed, then turn the fetched data
 101         into an instruction.
 102     */
 103     void processCacheCompletion(PacketPtr pkt);
 104
 105     /** Create request that will interface w/TLB and Memory objects */
 106     virtual void setupMemRequest(DynInstPtr inst, CacheReqPtr cache_req,
 107                                  int acc_size, int flags);
 108
 109     /** Align a PC to the start of an I-cache block. */
 110     Addr cacheBlockAlignPC(Addr addr)
 111     {
 112         return (addr & ~(cacheBlkMask));
 113     }
 114
 115     void removeAddrDependency(DynInstPtr inst);
 116
 117     std::list<FetchBlock*>::iterator findReplacementBlock();
 118     std::list<FetchBlock*>::iterator findBlock(std::list<FetchBlock*>
 119                                                &fetch_blocks, int asid,
 120                                                Addr block_addr);
 121
 122     void markBlockUsed(std::list<FetchBlock*>::iterator block_it);
 123
 124     int blocksInUse();
 125
 126     void clearFetchBuffer();
 127
 128     int instSize;
 129
 130     int fetchBuffSize;
 131
 132     TheISA::Predecoder *predecoder[ThePipeline::MaxThreads];
 133
 134     /** Valid Cache Blocks*/
 135     std::list<FetchBlock*> fetchBuffer;
 136
 137     /** Cache lines that are pending */
 138     std::list<FetchBlock*> pendingFetch;
 139 };
 140
 141 #endif //__CPU_FETCH_UNIT_HH__