merge
[gem5.git] / src / cpu / inorder / resources / graduation_unit.cc
1 /*
2 * Copyright (c) 2007 MIPS Technologies, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Korey Sewell
29 *
30 */
31
32 #include "cpu/inorder/resources/graduation_unit.hh"
33
34 using namespace ThePipeline;
35
36 GraduationUnit::GraduationUnit(std::string res_name, int res_id, int res_width,
37 int res_latency, InOrderCPU *_cpu, ThePipeline::Params *params)
38 : Resource(res_name, res_id, res_width, res_latency, _cpu),
39 lastCycleGrad(0), numCycleGrad(0)
40
41 {
42 for (ThreadID tid = 0; tid < ThePipeline::MaxThreads; tid++) {
43 nonSpecInstActive[tid] = &cpu->nonSpecInstActive[tid];
44 nonSpecSeqNum[tid] = &cpu->nonSpecSeqNum[tid];
45 }
46 }
47
48 void
49 GraduationUnit::execute(int slot_num)
50 {
51 ResourceRequest* grad_req = reqMap[slot_num];
52 DynInstPtr inst = reqMap[slot_num]->inst;
53 Fault fault = reqMap[slot_num]->fault;
54 ThreadID tid = inst->readTid();
55 int stage_num = inst->resSched.top()->stageNum;
56
57 grad_req->fault = NoFault;
58
59 switch (grad_req->cmd)
60 {
61 case GraduateInst:
62 {
63 // @TODO: Instructions should never really get to this point since this should be handled
64 // through the request interface. Check to make sure this happens and delete this
65 // code.
66 if (lastCycleGrad != curTick) {
67 lastCycleGrad = curTick;
68 numCycleGrad = 0;
69 } else if (numCycleGrad > width) {
70 DPRINTF(InOrderGraduation,
71 "Graduation bandwidth reached for this cycle.\n");
72 return;
73 }
74
75 // Make sure this is the last thing on the resource schedule
76 assert(inst->resSched.size() == 1);
77
78 DPRINTF(InOrderGraduation,
79 "[tid:%i] Graduating instruction [sn:%i].\n",
80 tid, inst->seqNum);
81
82 // Release Non-Speculative "Block" on instructions that could not execute
83 // because there was a non-speculative inst. active.
84 // @TODO: Fix this functionality. Probably too conservative.
85 if (inst->isNonSpeculative()) {
86 *nonSpecInstActive[tid] = false;
87 DPRINTF(InOrderGraduation,
88 "[tid:%i] Non-speculative inst [sn:%i] graduated\n",
89 tid, inst->seqNum);
90 }
91
92 if (inst->traceData) {
93 inst->traceData->setStageCycle(stage_num, curTick);
94 }
95
96 // Tell CPU that instruction is finished processing
97 cpu->instDone(inst, tid);
98
99 //cpu->pipelineStage[stage_num]->toPrevStages->
100 //stageInfo[stage_num][tid].doneSeqNum = inst->seqNum;
101
102 grad_req->done();
103 }
104 break;
105
106 default:
107 fatal("Unrecognized command to %s", resName);
108 }
109
110 }