2 * Copyright (c) 2007 MIPS Technologies, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Korey Sewell
32 #include "cpu/inorder/resources/graduation_unit.hh"
34 using namespace ThePipeline
;
36 GraduationUnit::GraduationUnit(std::string res_name
, int res_id
, int res_width
,
37 int res_latency
, InOrderCPU
*_cpu
,
38 ThePipeline::Params
*params
)
39 : Resource(res_name
, res_id
, res_width
, res_latency
, _cpu
),
40 lastCycleGrad(0), numCycleGrad(0)
43 for (ThreadID tid
= 0; tid
< ThePipeline::MaxThreads
; tid
++) {
44 nonSpecInstActive
[tid
] = &cpu
->nonSpecInstActive
[tid
];
45 nonSpecSeqNum
[tid
] = &cpu
->nonSpecSeqNum
[tid
];
50 GraduationUnit::execute(int slot_num
)
52 ResourceRequest
* grad_req
= reqMap
[slot_num
];
53 DynInstPtr inst
= reqMap
[slot_num
]->inst
;
54 Fault fault
= reqMap
[slot_num
]->fault
;
55 ThreadID tid
= inst
->readTid();
56 int stage_num
= inst
->resSched
.top()->stageNum
;
58 grad_req
->fault
= NoFault
;
60 switch (grad_req
->cmd
)
64 // @TODO: Instructions should never really get to this point since
65 // this should be handled through the request interface. Check to
66 // make sure this happens and delete this code.
67 if (lastCycleGrad
!= curTick()) {
68 lastCycleGrad
= curTick();
70 } else if (numCycleGrad
> width
) {
71 DPRINTF(InOrderGraduation
,
72 "Graduation bandwidth reached for this cycle.\n");
76 // Make sure this is the last thing on the resource schedule
77 assert(inst
->resSched
.size() == 1);
79 DPRINTF(InOrderGraduation
,
80 "[tid:%i] Graduating instruction [sn:%i].\n",
83 // Release Non-Speculative "Block" on instructions that could not
84 // execute because there was a non-speculative inst. active.
85 // @TODO: Fix this functionality. Probably too conservative.
86 if (inst
->isNonSpeculative()) {
87 *nonSpecInstActive
[tid
] = false;
88 DPRINTF(InOrderGraduation
,
89 "[tid:%i] Non-speculative inst [sn:%i] graduated\n",
93 if (inst
->traceData
) {
94 inst
->traceData
->setStageCycle(stage_num
, curTick());
97 // Tell CPU that instruction is finished processing
98 cpu
->instDone(inst
, tid
);
100 //cpu->pipelineStage[stage_num]->toPrevStages->
101 //stageInfo[stage_num][tid].doneSeqNum = inst->seqNum;
108 fatal("Unrecognized command to %s", resName
);