src/cpu/inorder/resources/inst_buffer.cc

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #include <list>
  33 #include <vector>
  34
  35 #include "arch/isa_traits.hh"
  36 #include "config/the_isa.hh"
  37 #include "cpu/inorder/resources/inst_buffer.hh"
  38 #include "cpu/inorder/cpu.hh"
  39 #include "cpu/inorder/pipeline_traits.hh"
  40 #include "debug/InOrderInstBuffer.hh"
  41 #include "debug/Resource.hh"
  42
  43 using namespace std;
  44 using namespace TheISA;
  45 using namespace ThePipeline;
  46
  47 InstBuffer::InstBuffer(string res_name, int res_id, int res_width,
  48                        int res_latency, InOrderCPU *_cpu,
  49                        ThePipeline::Params *params)
  50     : Resource(res_name, res_id, res_width, res_latency, _cpu)
  51 { }
  52
  53 void
  54 InstBuffer::regStats()
  55 {
  56     instsBypassed
  57         .name(name() + ".instsBypassed")
  58         .desc("Number of Instructions Bypassed.")
  59         .prereq(instsBypassed);
  60
  61     Resource::regStats();
  62 }
  63
  64 void
  65 InstBuffer::execute(int slot_idx)
  66 {
  67     ResReqPtr ib_req = reqs[slot_idx];
  68     DynInstPtr inst = ib_req->inst;
  69     ThreadID tid = inst->readTid();
  70     int stage_num = ib_req->getStageNum();
  71
  72     switch (ib_req->cmd)
  73     {
  74       case ScheduleOrBypass:
  75         {
  76             int next_stage = stage_num + 1;
  77             int bypass_stage = stage_num + 2;
  78             bool do_bypass = true;
  79
  80             if (!instList.empty()) {
  81                 DPRINTF(InOrderInstBuffer, "[sn:%i] cannot bypass stage %i "
  82                         "because buffer isn't empty.\n",
  83                         inst->seqNum, next_stage);
  84                 do_bypass = false;
  85             } else if(cpu->pipelineStage[bypass_stage]->isBlocked(tid)) {
  86                 DPRINTF(InOrderInstBuffer, "[sn:%i] cannot bypass stage %i "
  87                         "because stage %i is blocking.\n",
  88                         inst->seqNum, next_stage);
  89                 do_bypass = false;
  90             } else if(cpu->pipelineStage[bypass_stage]->
  91                       stageBufferAvail() <= 0) {
  92                 DPRINTF(InOrderInstBuffer, "[sn:%i] cannot bypass stage %i "
  93                         "because there is no room in stage %i incoming stage "
  94                         "buffer.\n", inst->seqNum, next_stage);
  95                 do_bypass = false;
  96             }
  97
  98             if (!do_bypass) { // SCHEDULE USAGE OF BUFFER
  99                 DPRINTF(InOrderInstBuffer, "Scheduling [sn:%i] for buffer "
 100                         "insertion in stage %i\n",
 101                         inst->seqNum, next_stage);
 102
 103                 // Add to schedule: Insert into buffer in next stage
 104                 int stage_pri = 20;
 105                 RSkedPtr insert_sked = (stage_num >= ThePipeline::BackEndStartStage) ?
 106                     inst->backSked : inst->frontSked;
 107
 108                 insert_sked->push(new ScheduleEntry(next_stage,
 109                                                       stage_pri,
 110                                                       id,
 111                                                       InstBuffer::InsertInst));
 112
 113                 // Add to schedule: Remove from buffer in next next (bypass)
 114                 // stage
 115                 stage_pri = 20;
 116                 RSkedPtr bypass_sked = (stage_num >= ThePipeline::BackEndStartStage) ?
 117                     inst->backSked : inst->frontSked;
 118
 119                bypass_sked->push(new ScheduleEntry(bypass_stage,
 120                                                       stage_pri,
 121                                                       id,
 122                                                       InstBuffer::RemoveInst));
 123             } else {         // BYPASS BUFFER & NEXT STAGE
 124                 DPRINTF(InOrderInstBuffer, "Setting [sn:%i] to bypass stage "
 125                         "%i and enter stage %i.\n", inst->seqNum, next_stage,
 126                         bypass_stage);
 127                 inst->setNextStage(bypass_stage);
 128                 instsBypassed++;
 129             }
 130
 131             ib_req->done();
 132         }
 133         break;
 134
 135       case InsertInst:
 136         {
 137             bool inserted = false;
 138
 139             if (instList.size() < width) {
 140                 DPRINTF(InOrderInstBuffer, "[tid:%i]: Inserting [sn:%i] into "
 141                         "buffer.\n", tid, inst->seqNum);
 142                 insert(inst);
 143                 inserted = true;
 144             } else {
 145                 DPRINTF(InOrderInstBuffer, "[tid:%i]: Denying [sn:%i] request "
 146                         "because buffer is full.\n", tid, inst->seqNum);
 147
 148
 149                 std::list<DynInstPtr>::iterator list_it = instList.begin();
 150                 std::list<DynInstPtr>::iterator list_end = instList.end();
 151
 152                 while (list_it != list_end) {
 153                     DPRINTF(Resource,"Serving [tid:%i] [sn:%i].\n",
 154                             (*list_it)->readTid(), (*list_it)->seqNum);
 155                     list_it++;
 156                 }
 157             }
 158
 159             ib_req->done(inserted);
 160         }
 161         break;
 162
 163       case RemoveInst:
 164         {
 165             DPRINTF(InOrderInstBuffer, "[tid:%i]: Removing [sn:%i] from "
 166                     "buffer.\n", tid, inst->seqNum);
 167             remove(inst);
 168             ib_req->done();
 169         }
 170         break;
 171
 172       default:
 173         fatal("Unrecognized command to %s", resName);
 174     }
 175
 176     DPRINTF(InOrderInstBuffer, "Buffer now contains %i insts.\n",
 177             instList.size());
 178 }
 179
 180 void
 181 InstBuffer::insert(DynInstPtr inst)
 182 {
 183     instList.push_back(inst);
 184 }
 185
 186 void
 187 InstBuffer::remove(DynInstPtr inst)
 188 {
 189     std::list<DynInstPtr>::iterator list_it = instList.begin();
 190     std::list<DynInstPtr>::iterator list_end = instList.end();
 191
 192     while (list_it != list_end) {
 193         if((*list_it) == inst) {
 194             instList.erase(list_it);
 195             break;
 196         }
 197         list_it++;
 198     }
 199 }
 200
 201 void
 202 InstBuffer::pop(ThreadID tid)
 203 {
 204     instList.pop_front();
 205 }
 206
 207 ThePipeline::DynInstPtr
 208 InstBuffer::top(ThreadID tid)
 209 {
 210     return instList.front();
 211 }
 212
 213 void
 214 InstBuffer::squash(DynInstPtr inst, int stage_num,
 215                    InstSeqNum squash_seq_num, ThreadID tid)
 216 {
 217     queue<list<DynInstPtr>::iterator> remove_list;
 218     list<DynInstPtr>::iterator list_it = instList.begin();
 219     list<DynInstPtr>::iterator list_end = instList.end();
 220
 221     // Collect All Instructions to be Removed in Remove List
 222     while (list_it != list_end) {
 223         if((*list_it)->readTid() == tid &&
 224            (*list_it)->seqNum > squash_seq_num) {
 225             (*list_it)->setSquashed();
 226             remove_list.push(list_it);
 227         }
 228
 229         list_it++;
 230     }
 231
 232     // Removed Instructions from InstList & Clear Remove List
 233     while (!remove_list.empty()) {
 234         DPRINTF(InOrderInstBuffer, "[tid:%i]: Removing squashed [sn:%i] from "
 235                 "buffer.\n", tid, (*remove_list.front())->seqNum);
 236         instList.erase(remove_list.front());
 237         remove_list.pop();
 238     }
 239
 240     Resource::squash(inst, stage_num, squash_seq_num, tid);
 241 }