src/cpu/inorder/resources/inst_buffer.cc

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #include <vector>
  33 #include <list>
  34
  35 #include "arch/isa_traits.hh"
  36 #include "config/the_isa.hh"
  37 #include "cpu/inorder/pipeline_traits.hh"
  38 #include "cpu/inorder/resources/inst_buffer.hh"
  39 #include "cpu/inorder/cpu.hh"
  40
  41 using namespace std;
  42 using namespace TheISA;
  43 using namespace ThePipeline;
  44
  45 InstBuffer::InstBuffer(string res_name, int res_id, int res_width,
  46                  int res_latency, InOrderCPU *_cpu, ThePipeline::Params *params)
  47     : Resource(res_name, res_id, res_width, res_latency, _cpu)
  48 { }
  49
  50 void
  51 InstBuffer::regStats()
  52 {
  53     instsBypassed
  54         .name(name() + ".instsBypassed")
  55         .desc("Number of Instructions Bypassed.")
  56         .prereq(instsBypassed);
  57
  58     Resource::regStats();
  59 }
  60
  61 void
  62 InstBuffer::execute(int slot_idx)
  63 {
  64     ResReqPtr ib_req = reqMap[slot_idx];
  65     DynInstPtr inst = ib_req->inst;
  66     ThreadID tid = inst->readTid();
  67     int stage_num = ib_req->getStageNum();
  68
  69     ib_req->fault = NoFault;
  70
  71     switch (ib_req->cmd)
  72     {
  73       case ScheduleOrBypass:
  74         {
  75             int next_stage = stage_num + 1;
  76             int bypass_stage = stage_num + 2;
  77             bool do_bypass = true;
  78
  79             if (!instList.empty()) {
  80                 DPRINTF(InOrderInstBuffer, "[sn:%i] cannot bypass stage %i because buffer isn't empty.\n",
  81                         inst->seqNum, next_stage);
  82                 do_bypass = false;
  83             } else if(cpu->pipelineStage[bypass_stage]->isBlocked(tid)) {
  84                 DPRINTF(InOrderInstBuffer, "[sn:%i] cannot bypass stage %i because stage %i is blocking.\n",
  85                         inst->seqNum, next_stage);
  86                 do_bypass = false;
  87             } else if(cpu->pipelineStage[bypass_stage]->stageBufferAvail() <= 0) {
  88                 DPRINTF(InOrderInstBuffer, "[sn:%i] cannot bypass stage %i because there is no room in "
  89                         "stage %i incoming stage buffer.\n", inst->seqNum, next_stage);
  90                 do_bypass = false;
  91             }
  92
  93             if (!do_bypass) { // SCHEDULE USAGE OF BUFFER
  94                 DPRINTF(InOrderInstBuffer, "Scheduling [sn:%i] for buffer insertion in stage %i\n",
  95                         inst->seqNum, next_stage);
  96
  97                 // Add to schedule: Insert into buffer in next stage
  98                 int stage_pri = ThePipeline::getNextPriority(inst, next_stage);
  99
 100                 inst->resSched.push(new ScheduleEntry(next_stage, stage_pri, id,
 101                                                    InstBuffer::InsertInst));
 102
 103                 // Add to schedule: Remove from buffer in next next (bypass) stage
 104                 stage_pri = ThePipeline::getNextPriority(inst, bypass_stage);
 105
 106                 inst->resSched.push(new ScheduleEntry(bypass_stage, stage_pri, id,
 107                                                    InstBuffer::RemoveInst));
 108             } else {         // BYPASS BUFFER & NEXT STAGE
 109                 DPRINTF(InOrderInstBuffer, "Setting [sn:%i] to bypass stage %i and enter stage %i.\n",
 110                         inst->seqNum, next_stage, bypass_stage);
 111                 inst->setNextStage(bypass_stage);
 112                 instsBypassed++;
 113             }
 114
 115             ib_req->done();
 116         }
 117         break;
 118
 119       case InsertInst:
 120         {
 121             bool inserted = false;
 122
 123             if (instList.size() < width) {
 124                 DPRINTF(InOrderInstBuffer, "[tid:%i]: Inserting [sn:%i] into buffer.\n",
 125                         tid, inst->seqNum);
 126                 insert(inst);
 127                 inserted = true;
 128             } else {
 129                 DPRINTF(InOrderInstBuffer, "[tid:%i]: Denying [sn:%i] request because "
 130                         "buffer is full.\n", tid, inst->seqNum);
 131
 132
 133                 std::list<DynInstPtr>::iterator list_it = instList.begin();
 134                 std::list<DynInstPtr>::iterator list_end = instList.end();
 135
 136                 while (list_it != list_end) {
 137                     DPRINTF(Resource,"Serving [tid:%i] [sn:%i].\n", (*list_it)->readTid(), (*list_it)->seqNum);
 138                     list_it++;
 139                 }
 140             }
 141
 142             ib_req->done(inserted);
 143         }
 144         break;
 145
 146       case RemoveInst:
 147         {
 148             DPRINTF(InOrderInstBuffer, "[tid:%i]: Removing [sn:%i] from buffer.\n",
 149                     tid, inst->seqNum);
 150             remove(inst);
 151             ib_req->done();
 152         }
 153         break;
 154
 155       default:
 156         fatal("Unrecognized command to %s", resName);
 157     }
 158
 159     DPRINTF(InOrderInstBuffer, "Buffer now contains %i insts.\n", instList.size());
 160 }
 161
 162 void
 163 InstBuffer::insert(DynInstPtr inst)
 164 {
 165     instList.push_back(inst);
 166 }
 167
 168 void
 169 InstBuffer::remove(DynInstPtr inst)
 170 {
 171     std::list<DynInstPtr>::iterator list_it = instList.begin();
 172     std::list<DynInstPtr>::iterator list_end = instList.end();
 173
 174     while (list_it != list_end) {
 175         if((*list_it) == inst) {
 176             instList.erase(list_it);
 177             break;
 178         }
 179         list_it++;
 180     }
 181 }
 182
 183 void
 184 InstBuffer::pop(ThreadID tid)
 185 {
 186     instList.pop_front();
 187 }
 188
 189 ThePipeline::DynInstPtr
 190 InstBuffer::top(ThreadID tid)
 191 {
 192     return instList.front();
 193 }
 194
 195 void
 196 InstBuffer::squash(DynInstPtr inst, int stage_num,
 197                    InstSeqNum squash_seq_num, ThreadID tid)
 198 {
 199     queue<list<DynInstPtr>::iterator> remove_list;
 200     list<DynInstPtr>::iterator list_it = instList.begin();
 201     list<DynInstPtr>::iterator list_end = instList.end();
 202
 203     // Collect All Instructions to be Removed in Remove List
 204     while (list_it != list_end) {
 205         if((*list_it)->readTid() == tid &&
 206            (*list_it)->seqNum > squash_seq_num) {
 207             (*list_it)->setSquashed();
 208             remove_list.push(list_it);
 209         }
 210
 211         list_it++;
 212     }
 213
 214     // Removed Instructions from InstList & Clear Remove List
 215     while (!remove_list.empty()) {
 216         DPRINTF(InOrderInstBuffer, "[tid:%i]: Removing squashed [sn:%i] from buffer.\n",
 217                 tid, (*remove_list.front())->seqNum);
 218         instList.erase(remove_list.front());
 219         remove_list.pop();
 220     }
 221
 222     Resource::squash(inst, stage_num, squash_seq_num, tid);
 223 }