src/cpu/inorder/resources/inst_buffer.cc

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #include <vector>
  33 #include <list>
  34 #include "arch/isa_traits.hh"
  35 #include "cpu/inorder/pipeline_traits.hh"
  36 #include "cpu/inorder/resources/inst_buffer.hh"
  37 #include "cpu/inorder/cpu.hh"
  38
  39 using namespace std;
  40 using namespace TheISA;
  41 using namespace ThePipeline;
  42
  43 InstBuffer::InstBuffer(string res_name, int res_id, int res_width,
  44                  int res_latency, InOrderCPU *_cpu, ThePipeline::Params *params)
  45     : Resource(res_name, res_id, res_width, res_latency, _cpu)
  46 { }
  47
  48 void
  49 InstBuffer::regStats()
  50 {
  51     instsBypassed
  52         .name(name() + ".instsBypassed")
  53         .desc("Number of Instructions Bypassed.");
  54
  55     Resource::regStats();
  56 }
  57
  58 void
  59 InstBuffer::execute(int slot_idx)
  60 {
  61     ResReqPtr ib_req = reqMap[slot_idx];
  62     DynInstPtr inst = ib_req->inst;
  63     int tid, seq_num, stage_num;
  64
  65     tid = inst->readTid();
  66     seq_num = inst->seqNum;
  67     stage_num = ib_req->getStageNum();
  68     ib_req->fault = NoFault;
  69
  70     switch (ib_req->cmd)
  71     {
  72       case ScheduleOrBypass:
  73         {
  74             int next_stage = stage_num + 1;
  75             int bypass_stage = stage_num + 2;
  76             bool do_bypass = true;
  77
  78             if (!instList.empty()) {
  79                 DPRINTF(Resource, "[sn:%i] cannot bypass stage %i because buffer isn't empty.\n",
  80                         inst->seqNum, next_stage);
  81                 do_bypass = false;
  82             } else if(cpu->pipelineStage[bypass_stage]->isBlocked(tid)) {
  83                 DPRINTF(Resource, "[sn:%i] cannot bypass stage %i because stage %i is blocking.\n",
  84                         inst->seqNum, next_stage);
  85                 do_bypass = false;
  86             } else if(cpu->pipelineStage[bypass_stage]->stageBufferAvail() <= 0) {
  87                 DPRINTF(Resource, "[sn:%i] cannot bypass stage %i because there is no room in "
  88                         "stage %i incoming stage buffer.\n", inst->seqNum, next_stage);
  89                 do_bypass = false;
  90             }
  91
  92             if (!do_bypass) { // SCHEDULE USAGE OF BUFFER
  93                 DPRINTF(Resource, "Scheduling [sn:%i] for buffer insertion in stage %i\n",
  94                         inst->seqNum, next_stage);
  95
  96                 // Add to schedule: Insert into buffer in next stage
  97                 int stage_pri = ThePipeline::getNextPriority(inst, next_stage);
  98
  99                 inst->resSched.push(new ScheduleEntry(next_stage, stage_pri, id,
 100                                                    InstBuffer::InsertInst));
 101
 102                 // Add to schedule: Remove from buffer in next next (bypass) stage
 103                 stage_pri = ThePipeline::getNextPriority(inst, bypass_stage);
 104
 105                 inst->resSched.push(new ScheduleEntry(bypass_stage, stage_pri, id,
 106                                                    InstBuffer::RemoveInst));
 107             } else {         // BYPASS BUFFER & NEXT STAGE
 108                 DPRINTF(Resource, "Setting [sn:%i] to bypass stage %i and enter stage %i.\n",
 109                         inst->seqNum, next_stage, bypass_stage);
 110                 inst->setNextStage(bypass_stage);
 111                 instsBypassed++;
 112             }
 113
 114             ib_req->done();
 115         }
 116         break;
 117
 118       case InsertInst:
 119         {
 120             bool inserted = false;
 121
 122             if (instList.size() < width) {
 123                 DPRINTF(Resource, "[tid:%i]: Inserting [sn:%i] into buffer.\n",
 124                         tid, seq_num);
 125                 insert(inst);
 126                 inserted = true;
 127             } else {
 128                 DPRINTF(Resource, "[tid:%i]: Denying [sn:%i] request because "
 129                         "buffer is full.\n", tid, seq_num);
 130
 131
 132                 std::list<DynInstPtr>::iterator list_it = instList.begin();
 133                 std::list<DynInstPtr>::iterator list_end = instList.end();
 134
 135                 while (list_it != list_end) {
 136                     DPRINTF(Resource,"Serving [tid:%i] [sn:%i].\n", (*list_it)->readTid(), (*list_it)->seqNum);
 137                     list_it++;
 138                 }
 139             }
 140
 141             ib_req->done(inserted);
 142         }
 143         break;
 144
 145       case RemoveInst:
 146         {
 147             DPRINTF(Resource, "[tid:%i]: Removing [sn:%i] from buffer.\n",
 148                     tid, seq_num);
 149             remove(inst);
 150             ib_req->done();
 151         }
 152         break;
 153
 154       default:
 155         fatal("Unrecognized command to %s", resName);
 156     }
 157
 158     DPRINTF(Resource, "Buffer now contains %i insts.\n", instList.size());
 159 }
 160
 161 void
 162 InstBuffer::insert(DynInstPtr inst)
 163 {
 164     instList.push_back(inst);
 165 }
 166
 167 void
 168 InstBuffer::remove(DynInstPtr inst)
 169 {
 170     std::list<DynInstPtr>::iterator list_it = instList.begin();
 171     std::list<DynInstPtr>::iterator list_end = instList.end();
 172
 173     while (list_it != list_end) {
 174         if((*list_it) == inst) {
 175             instList.erase(list_it);
 176             break;
 177         }
 178         list_it++;
 179     }
 180 }
 181
 182 void
 183 InstBuffer::pop(unsigned tid)
 184 {
 185     instList.pop_front();
 186 }
 187
 188 ThePipeline::DynInstPtr
 189 InstBuffer::top(unsigned tid)
 190 {
 191     return instList.front();
 192 }
 193
 194 void
 195 InstBuffer::squash(DynInstPtr inst, int stage_num,
 196                    InstSeqNum squash_seq_num, unsigned tid)
 197 {
 198     queue<list<DynInstPtr>::iterator> remove_list;
 199     list<DynInstPtr>::iterator list_it = instList.begin();
 200     list<DynInstPtr>::iterator list_end = instList.end();
 201
 202     // Collect All Instructions to be Removed in Remove List
 203     while (list_it != list_end) {
 204         if((*list_it)->readTid() == tid &&
 205            (*list_it)->seqNum > squash_seq_num) {
 206             (*list_it)->setSquashed();
 207             remove_list.push(list_it);
 208         }
 209
 210         list_it++;
 211     }
 212
 213     // Removed Instructions from InstList & Clear Remove List
 214     while (!remove_list.empty()) {
 215         DPRINTF(Resource, "[tid:%i]: Removing squashed [sn:%i] from buffer.\n",
 216                 tid, (*remove_list.front())->seqNum);
 217         instList.erase(remove_list.front());
 218         remove_list.pop();
 219     }
 220
 221     Resource::squash(inst, stage_num, squash_seq_num, tid);
 222 }