src/cpu/inorder/resources/inst_buffer.cc

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #include <vector>
  33 #include <list>
  34
  35 #include "arch/isa_traits.hh"
  36 #include "config/the_isa.hh"
  37 #include "cpu/inorder/pipeline_traits.hh"
  38 #include "cpu/inorder/resources/inst_buffer.hh"
  39 #include "cpu/inorder/cpu.hh"
  40
  41 using namespace std;
  42 using namespace TheISA;
  43 using namespace ThePipeline;
  44
  45 InstBuffer::InstBuffer(string res_name, int res_id, int res_width,
  46                        int res_latency, InOrderCPU *_cpu,
  47                        ThePipeline::Params *params)
  48     : Resource(res_name, res_id, res_width, res_latency, _cpu)
  49 { }
  50
  51 void
  52 InstBuffer::regStats()
  53 {
  54     instsBypassed
  55         .name(name() + ".instsBypassed")
  56         .desc("Number of Instructions Bypassed.")
  57         .prereq(instsBypassed);
  58
  59     Resource::regStats();
  60 }
  61
  62 void
  63 InstBuffer::execute(int slot_idx)
  64 {
  65     ResReqPtr ib_req = reqs[slot_idx];
  66     DynInstPtr inst = ib_req->inst;
  67     ThreadID tid = inst->readTid();
  68     int stage_num = ib_req->getStageNum();
  69
  70     switch (ib_req->cmd)
  71     {
  72       case ScheduleOrBypass:
  73         {
  74             int next_stage = stage_num + 1;
  75             int bypass_stage = stage_num + 2;
  76             bool do_bypass = true;
  77
  78             if (!instList.empty()) {
  79                 DPRINTF(InOrderInstBuffer, "[sn:%i] cannot bypass stage %i "
  80                         "because buffer isn't empty.\n",
  81                         inst->seqNum, next_stage);
  82                 do_bypass = false;
  83             } else if(cpu->pipelineStage[bypass_stage]->isBlocked(tid)) {
  84                 DPRINTF(InOrderInstBuffer, "[sn:%i] cannot bypass stage %i "
  85                         "because stage %i is blocking.\n",
  86                         inst->seqNum, next_stage);
  87                 do_bypass = false;
  88             } else if(cpu->pipelineStage[bypass_stage]->
  89                       stageBufferAvail() <= 0) {
  90                 DPRINTF(InOrderInstBuffer, "[sn:%i] cannot bypass stage %i "
  91                         "because there is no room in stage %i incoming stage "
  92                         "buffer.\n", inst->seqNum, next_stage);
  93                 do_bypass = false;
  94             }
  95
  96             if (!do_bypass) { // SCHEDULE USAGE OF BUFFER
  97                 DPRINTF(InOrderInstBuffer, "Scheduling [sn:%i] for buffer "
  98                         "insertion in stage %i\n",
  99                         inst->seqNum, next_stage);
 100
 101                 // Add to schedule: Insert into buffer in next stage
 102                 int stage_pri = 20;
 103                 RSkedPtr insert_sked = (stage_num >= ThePipeline::BackEndStartStage) ?
 104                     inst->backSked : inst->frontSked;
 105
 106                 insert_sked->push(new ScheduleEntry(next_stage,
 107                                                       stage_pri,
 108                                                       id,
 109                                                       InstBuffer::InsertInst));
 110
 111                 // Add to schedule: Remove from buffer in next next (bypass)
 112                 // stage
 113                 stage_pri = 20;
 114                 RSkedPtr bypass_sked = (stage_num >= ThePipeline::BackEndStartStage) ?
 115                     inst->backSked : inst->frontSked;
 116
 117                bypass_sked->push(new ScheduleEntry(bypass_stage,
 118                                                       stage_pri,
 119                                                       id,
 120                                                       InstBuffer::RemoveInst));
 121             } else {         // BYPASS BUFFER & NEXT STAGE
 122                 DPRINTF(InOrderInstBuffer, "Setting [sn:%i] to bypass stage "
 123                         "%i and enter stage %i.\n", inst->seqNum, next_stage,
 124                         bypass_stage);
 125                 inst->setNextStage(bypass_stage);
 126                 instsBypassed++;
 127             }
 128
 129             ib_req->done();
 130         }
 131         break;
 132
 133       case InsertInst:
 134         {
 135             bool inserted = false;
 136
 137             if (instList.size() < width) {
 138                 DPRINTF(InOrderInstBuffer, "[tid:%i]: Inserting [sn:%i] into "
 139                         "buffer.\n", tid, inst->seqNum);
 140                 insert(inst);
 141                 inserted = true;
 142             } else {
 143                 DPRINTF(InOrderInstBuffer, "[tid:%i]: Denying [sn:%i] request "
 144                         "because buffer is full.\n", tid, inst->seqNum);
 145
 146
 147                 std::list<DynInstPtr>::iterator list_it = instList.begin();
 148                 std::list<DynInstPtr>::iterator list_end = instList.end();
 149
 150                 while (list_it != list_end) {
 151                     DPRINTF(Resource,"Serving [tid:%i] [sn:%i].\n",
 152                             (*list_it)->readTid(), (*list_it)->seqNum);
 153                     list_it++;
 154                 }
 155             }
 156
 157             ib_req->done(inserted);
 158         }
 159         break;
 160
 161       case RemoveInst:
 162         {
 163             DPRINTF(InOrderInstBuffer, "[tid:%i]: Removing [sn:%i] from "
 164                     "buffer.\n", tid, inst->seqNum);
 165             remove(inst);
 166             ib_req->done();
 167         }
 168         break;
 169
 170       default:
 171         fatal("Unrecognized command to %s", resName);
 172     }
 173
 174     DPRINTF(InOrderInstBuffer, "Buffer now contains %i insts.\n",
 175             instList.size());
 176 }
 177
 178 void
 179 InstBuffer::insert(DynInstPtr inst)
 180 {
 181     instList.push_back(inst);
 182 }
 183
 184 void
 185 InstBuffer::remove(DynInstPtr inst)
 186 {
 187     std::list<DynInstPtr>::iterator list_it = instList.begin();
 188     std::list<DynInstPtr>::iterator list_end = instList.end();
 189
 190     while (list_it != list_end) {
 191         if((*list_it) == inst) {
 192             instList.erase(list_it);
 193             break;
 194         }
 195         list_it++;
 196     }
 197 }
 198
 199 void
 200 InstBuffer::pop(ThreadID tid)
 201 {
 202     instList.pop_front();
 203 }
 204
 205 ThePipeline::DynInstPtr
 206 InstBuffer::top(ThreadID tid)
 207 {
 208     return instList.front();
 209 }
 210
 211 void
 212 InstBuffer::squash(DynInstPtr inst, int stage_num,
 213                    InstSeqNum squash_seq_num, ThreadID tid)
 214 {
 215     queue<list<DynInstPtr>::iterator> remove_list;
 216     list<DynInstPtr>::iterator list_it = instList.begin();
 217     list<DynInstPtr>::iterator list_end = instList.end();
 218
 219     // Collect All Instructions to be Removed in Remove List
 220     while (list_it != list_end) {
 221         if((*list_it)->readTid() == tid &&
 222            (*list_it)->seqNum > squash_seq_num) {
 223             (*list_it)->setSquashed();
 224             remove_list.push(list_it);
 225         }
 226
 227         list_it++;
 228     }
 229
 230     // Removed Instructions from InstList & Clear Remove List
 231     while (!remove_list.empty()) {
 232         DPRINTF(InOrderInstBuffer, "[tid:%i]: Removing squashed [sn:%i] from "
 233                 "buffer.\n", tid, (*remove_list.front())->seqNum);
 234         instList.erase(remove_list.front());
 235         remove_list.pop();
 236     }
 237
 238     Resource::squash(inst, stage_num, squash_seq_num, tid);
 239 }