src/cpu/inorder/resources/inst_buffer.cc

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #include <vector>
  33 #include <list>
  34
  35 #include "arch/isa_traits.hh"
  36 #include "config/the_isa.hh"
  37 #include "cpu/inorder/pipeline_traits.hh"
  38 #include "cpu/inorder/resources/inst_buffer.hh"
  39 #include "cpu/inorder/cpu.hh"
  40
  41 using namespace std;
  42 using namespace TheISA;
  43 using namespace ThePipeline;
  44
  45 InstBuffer::InstBuffer(string res_name, int res_id, int res_width,
  46                        int res_latency, InOrderCPU *_cpu,
  47                        ThePipeline::Params *params)
  48     : Resource(res_name, res_id, res_width, res_latency, _cpu)
  49 { }
  50
  51 void
  52 InstBuffer::regStats()
  53 {
  54     instsBypassed
  55         .name(name() + ".instsBypassed")
  56         .desc("Number of Instructions Bypassed.")
  57         .prereq(instsBypassed);
  58
  59     Resource::regStats();
  60 }
  61
  62 void
  63 InstBuffer::execute(int slot_idx)
  64 {
  65     ResReqPtr ib_req = reqMap[slot_idx];
  66     DynInstPtr inst = ib_req->inst;
  67     ThreadID tid = inst->readTid();
  68     int stage_num = ib_req->getStageNum();
  69
  70     switch (ib_req->cmd)
  71     {
  72       case ScheduleOrBypass:
  73         {
  74             int next_stage = stage_num + 1;
  75             int bypass_stage = stage_num + 2;
  76             bool do_bypass = true;
  77
  78             if (!instList.empty()) {
  79                 DPRINTF(InOrderInstBuffer, "[sn:%i] cannot bypass stage %i "
  80                         "because buffer isn't empty.\n",
  81                         inst->seqNum, next_stage);
  82                 do_bypass = false;
  83             } else if(cpu->pipelineStage[bypass_stage]->isBlocked(tid)) {
  84                 DPRINTF(InOrderInstBuffer, "[sn:%i] cannot bypass stage %i "
  85                         "because stage %i is blocking.\n",
  86                         inst->seqNum, next_stage);
  87                 do_bypass = false;
  88             } else if(cpu->pipelineStage[bypass_stage]->
  89                       stageBufferAvail() <= 0) {
  90                 DPRINTF(InOrderInstBuffer, "[sn:%i] cannot bypass stage %i "
  91                         "because there is no room in stage %i incoming stage "
  92                         "buffer.\n", inst->seqNum, next_stage);
  93                 do_bypass = false;
  94             }
  95
  96             if (!do_bypass) { // SCHEDULE USAGE OF BUFFER
  97                 DPRINTF(InOrderInstBuffer, "Scheduling [sn:%i] for buffer "
  98                         "insertion in stage %i\n",
  99                         inst->seqNum, next_stage);
 100
 101                 // Add to schedule: Insert into buffer in next stage
 102                 int stage_pri = ThePipeline::getNextPriority(inst,
 103                                                              next_stage);
 104
 105                 inst->resSched.push(new ScheduleEntry(next_stage,
 106                                                       stage_pri,
 107                                                       id,
 108                                                       InstBuffer::InsertInst));
 109
 110                 // Add to schedule: Remove from buffer in next next (bypass)
 111                 // stage
 112                 stage_pri = ThePipeline::getNextPriority(inst, bypass_stage);
 113
 114                 inst->resSched.push(new ScheduleEntry(bypass_stage,
 115                                                       stage_pri,
 116                                                       id,
 117                                                       InstBuffer::RemoveInst));
 118             } else {         // BYPASS BUFFER & NEXT STAGE
 119                 DPRINTF(InOrderInstBuffer, "Setting [sn:%i] to bypass stage "
 120                         "%i and enter stage %i.\n", inst->seqNum, next_stage,
 121                         bypass_stage);
 122                 inst->setNextStage(bypass_stage);
 123                 instsBypassed++;
 124             }
 125
 126             ib_req->done();
 127         }
 128         break;
 129
 130       case InsertInst:
 131         {
 132             bool inserted = false;
 133
 134             if (instList.size() < width) {
 135                 DPRINTF(InOrderInstBuffer, "[tid:%i]: Inserting [sn:%i] into "
 136                         "buffer.\n", tid, inst->seqNum);
 137                 insert(inst);
 138                 inserted = true;
 139             } else {
 140                 DPRINTF(InOrderInstBuffer, "[tid:%i]: Denying [sn:%i] request "
 141                         "because buffer is full.\n", tid, inst->seqNum);
 142
 143
 144                 std::list<DynInstPtr>::iterator list_it = instList.begin();
 145                 std::list<DynInstPtr>::iterator list_end = instList.end();
 146
 147                 while (list_it != list_end) {
 148                     DPRINTF(Resource,"Serving [tid:%i] [sn:%i].\n",
 149                             (*list_it)->readTid(), (*list_it)->seqNum);
 150                     list_it++;
 151                 }
 152             }
 153
 154             ib_req->done(inserted);
 155         }
 156         break;
 157
 158       case RemoveInst:
 159         {
 160             DPRINTF(InOrderInstBuffer, "[tid:%i]: Removing [sn:%i] from "
 161                     "buffer.\n", tid, inst->seqNum);
 162             remove(inst);
 163             ib_req->done();
 164         }
 165         break;
 166
 167       default:
 168         fatal("Unrecognized command to %s", resName);
 169     }
 170
 171     DPRINTF(InOrderInstBuffer, "Buffer now contains %i insts.\n",
 172             instList.size());
 173 }
 174
 175 void
 176 InstBuffer::insert(DynInstPtr inst)
 177 {
 178     instList.push_back(inst);
 179 }
 180
 181 void
 182 InstBuffer::remove(DynInstPtr inst)
 183 {
 184     std::list<DynInstPtr>::iterator list_it = instList.begin();
 185     std::list<DynInstPtr>::iterator list_end = instList.end();
 186
 187     while (list_it != list_end) {
 188         if((*list_it) == inst) {
 189             instList.erase(list_it);
 190             break;
 191         }
 192         list_it++;
 193     }
 194 }
 195
 196 void
 197 InstBuffer::pop(ThreadID tid)
 198 {
 199     instList.pop_front();
 200 }
 201
 202 ThePipeline::DynInstPtr
 203 InstBuffer::top(ThreadID tid)
 204 {
 205     return instList.front();
 206 }
 207
 208 void
 209 InstBuffer::squash(DynInstPtr inst, int stage_num,
 210                    InstSeqNum squash_seq_num, ThreadID tid)
 211 {
 212     queue<list<DynInstPtr>::iterator> remove_list;
 213     list<DynInstPtr>::iterator list_it = instList.begin();
 214     list<DynInstPtr>::iterator list_end = instList.end();
 215
 216     // Collect All Instructions to be Removed in Remove List
 217     while (list_it != list_end) {
 218         if((*list_it)->readTid() == tid &&
 219            (*list_it)->seqNum > squash_seq_num) {
 220             (*list_it)->setSquashed();
 221             remove_list.push(list_it);
 222         }
 223
 224         list_it++;
 225     }
 226
 227     // Removed Instructions from InstList & Clear Remove List
 228     while (!remove_list.empty()) {
 229         DPRINTF(InOrderInstBuffer, "[tid:%i]: Removing squashed [sn:%i] from "
 230                 "buffer.\n", tid, (*remove_list.front())->seqNum);
 231         instList.erase(remove_list.front());
 232         remove_list.pop();
 233     }
 234
 235     Resource::squash(inst, stage_num, squash_seq_num, tid);
 236 }