src/cpu/inorder/resources/inst_buffer.cc

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #include <vector>
  33 #include <list>
  34
  35 #include "arch/isa_traits.hh"
  36 #include "config/the_isa.hh"
  37 #include "cpu/inorder/pipeline_traits.hh"
  38 #include "cpu/inorder/resources/inst_buffer.hh"
  39 #include "cpu/inorder/cpu.hh"
  40
  41 using namespace std;
  42 using namespace TheISA;
  43 using namespace ThePipeline;
  44
  45 InstBuffer::InstBuffer(string res_name, int res_id, int res_width,
  46                        int res_latency, InOrderCPU *_cpu,
  47                        ThePipeline::Params *params)
  48     : Resource(res_name, res_id, res_width, res_latency, _cpu)
  49 { }
  50
  51 void
  52 InstBuffer::regStats()
  53 {
  54     instsBypassed
  55         .name(name() + ".instsBypassed")
  56         .desc("Number of Instructions Bypassed.")
  57         .prereq(instsBypassed);
  58
  59     Resource::regStats();
  60 }
  61
  62 void
  63 InstBuffer::execute(int slot_idx)
  64 {
  65     ResReqPtr ib_req = reqMap[slot_idx];
  66     DynInstPtr inst = ib_req->inst;
  67     ThreadID tid = inst->readTid();
  68     int stage_num = ib_req->getStageNum();
  69
  70     ib_req->fault = NoFault;
  71
  72     switch (ib_req->cmd)
  73     {
  74       case ScheduleOrBypass:
  75         {
  76             int next_stage = stage_num + 1;
  77             int bypass_stage = stage_num + 2;
  78             bool do_bypass = true;
  79
  80             if (!instList.empty()) {
  81                 DPRINTF(InOrderInstBuffer, "[sn:%i] cannot bypass stage %i "
  82                         "because buffer isn't empty.\n",
  83                         inst->seqNum, next_stage);
  84                 do_bypass = false;
  85             } else if(cpu->pipelineStage[bypass_stage]->isBlocked(tid)) {
  86                 DPRINTF(InOrderInstBuffer, "[sn:%i] cannot bypass stage %i "
  87                         "because stage %i is blocking.\n",
  88                         inst->seqNum, next_stage);
  89                 do_bypass = false;
  90             } else if(cpu->pipelineStage[bypass_stage]->
  91                       stageBufferAvail() <= 0) {
  92                 DPRINTF(InOrderInstBuffer, "[sn:%i] cannot bypass stage %i "
  93                         "because there is no room in stage %i incoming stage "
  94                         "buffer.\n", inst->seqNum, next_stage);
  95                 do_bypass = false;
  96             }
  97
  98             if (!do_bypass) { // SCHEDULE USAGE OF BUFFER
  99                 DPRINTF(InOrderInstBuffer, "Scheduling [sn:%i] for buffer "
 100                         "insertion in stage %i\n",
 101                         inst->seqNum, next_stage);
 102
 103                 // Add to schedule: Insert into buffer in next stage
 104                 int stage_pri = ThePipeline::getNextPriority(inst,
 105                                                              next_stage);
 106
 107                 inst->resSched.push(new ScheduleEntry(next_stage,
 108                                                       stage_pri,
 109                                                       id,
 110                                                       InstBuffer::InsertInst));
 111
 112                 // Add to schedule: Remove from buffer in next next (bypass)
 113                 // stage
 114                 stage_pri = ThePipeline::getNextPriority(inst, bypass_stage);
 115
 116                 inst->resSched.push(new ScheduleEntry(bypass_stage,
 117                                                       stage_pri,
 118                                                       id,
 119                                                       InstBuffer::RemoveInst));
 120             } else {         // BYPASS BUFFER & NEXT STAGE
 121                 DPRINTF(InOrderInstBuffer, "Setting [sn:%i] to bypass stage "
 122                         "%i and enter stage %i.\n", inst->seqNum, next_stage,
 123                         bypass_stage);
 124                 inst->setNextStage(bypass_stage);
 125                 instsBypassed++;
 126             }
 127
 128             ib_req->done();
 129         }
 130         break;
 131
 132       case InsertInst:
 133         {
 134             bool inserted = false;
 135
 136             if (instList.size() < width) {
 137                 DPRINTF(InOrderInstBuffer, "[tid:%i]: Inserting [sn:%i] into "
 138                         "buffer.\n", tid, inst->seqNum);
 139                 insert(inst);
 140                 inserted = true;
 141             } else {
 142                 DPRINTF(InOrderInstBuffer, "[tid:%i]: Denying [sn:%i] request "
 143                         "because buffer is full.\n", tid, inst->seqNum);
 144
 145
 146                 std::list<DynInstPtr>::iterator list_it = instList.begin();
 147                 std::list<DynInstPtr>::iterator list_end = instList.end();
 148
 149                 while (list_it != list_end) {
 150                     DPRINTF(Resource,"Serving [tid:%i] [sn:%i].\n",
 151                             (*list_it)->readTid(), (*list_it)->seqNum);
 152                     list_it++;
 153                 }
 154             }
 155
 156             ib_req->done(inserted);
 157         }
 158         break;
 159
 160       case RemoveInst:
 161         {
 162             DPRINTF(InOrderInstBuffer, "[tid:%i]: Removing [sn:%i] from "
 163                     "buffer.\n", tid, inst->seqNum);
 164             remove(inst);
 165             ib_req->done();
 166         }
 167         break;
 168
 169       default:
 170         fatal("Unrecognized command to %s", resName);
 171     }
 172
 173     DPRINTF(InOrderInstBuffer, "Buffer now contains %i insts.\n",
 174             instList.size());
 175 }
 176
 177 void
 178 InstBuffer::insert(DynInstPtr inst)
 179 {
 180     instList.push_back(inst);
 181 }
 182
 183 void
 184 InstBuffer::remove(DynInstPtr inst)
 185 {
 186     std::list<DynInstPtr>::iterator list_it = instList.begin();
 187     std::list<DynInstPtr>::iterator list_end = instList.end();
 188
 189     while (list_it != list_end) {
 190         if((*list_it) == inst) {
 191             instList.erase(list_it);
 192             break;
 193         }
 194         list_it++;
 195     }
 196 }
 197
 198 void
 199 InstBuffer::pop(ThreadID tid)
 200 {
 201     instList.pop_front();
 202 }
 203
 204 ThePipeline::DynInstPtr
 205 InstBuffer::top(ThreadID tid)
 206 {
 207     return instList.front();
 208 }
 209
 210 void
 211 InstBuffer::squash(DynInstPtr inst, int stage_num,
 212                    InstSeqNum squash_seq_num, ThreadID tid)
 213 {
 214     queue<list<DynInstPtr>::iterator> remove_list;
 215     list<DynInstPtr>::iterator list_it = instList.begin();
 216     list<DynInstPtr>::iterator list_end = instList.end();
 217
 218     // Collect All Instructions to be Removed in Remove List
 219     while (list_it != list_end) {
 220         if((*list_it)->readTid() == tid &&
 221            (*list_it)->seqNum > squash_seq_num) {
 222             (*list_it)->setSquashed();
 223             remove_list.push(list_it);
 224         }
 225
 226         list_it++;
 227     }
 228
 229     // Removed Instructions from InstList & Clear Remove List
 230     while (!remove_list.empty()) {
 231         DPRINTF(InOrderInstBuffer, "[tid:%i]: Removing squashed [sn:%i] from "
 232                 "buffer.\n", tid, (*remove_list.front())->seqNum);
 233         instList.erase(remove_list.front());
 234         remove_list.pop();
 235     }
 236
 237     Resource::squash(inst, stage_num, squash_seq_num, tid);
 238 }