2 * Copyright (c) 2007 MIPS Technologies, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Korey Sewell
32 #ifndef __CPU_INORDER_MULT_DIV_UNIT_HH__
33 #define __CPU_INORDER_MULT_DIV_UNIT_HH__
39 #include "cpu/func_unit.hh"
40 #include "cpu/op_class.hh"
41 #include "cpu/inorder/first_stage.hh"
42 #include "cpu/inorder/resource.hh"
43 #include "cpu/inorder/inorder_dyn_inst.hh"
47 class MultDivUnit : public Resource {
49 typedef ThePipeline::DynInstPtr DynInstPtr;
58 MultDivUnit(std::string res_name, int res_id, int res_width,
59 int res_latency, InOrderCPU *_cpu, ThePipeline::Params *params);
60 virtual ~MultDivUnit() {}
63 /** Override default Resource getSlot(). Will only getSlot if
64 * valid mult/div sequence is being maintained
66 virtual int getSlot(DynInstPtr inst);
68 virtual int findSlot(DynInstPtr inst);
70 virtual void freeSlot(int slot_idx);
74 /** Get Operand Size For A Division Operation */
75 int getDivOpSize(DynInstPtr inst);
77 /** Override default Resource execute */
78 virtual void execute(int slot_num);
80 void exeMulDiv(int slot_num);
82 /** Register extra resource stats */
83 virtual void regStats();
85 void requestAgain(DynInstPtr inst, bool &try_request);
88 /** Latency & Repeat Rate for Multiply Insts */
89 unsigned multRepeatRate;
92 /** Latency & Repeat Rate for 8-bit Divide Insts */
93 unsigned div8RepeatRate;
96 /** Latency & Repeat Rate for 16-bit Divide Insts */
97 unsigned div16RepeatRate;
98 unsigned div16Latency;
100 /** Latency & Repeat Rate for 24-bit Divide Insts */
101 unsigned div24RepeatRate;
102 unsigned div24Latency;
104 /** Latency & Repeat Rate for 32-bit Divide Insts */
105 unsigned div32RepeatRate;
106 unsigned div32Latency;
108 /** Last cycle that MDU was used */
111 /** Last type of instruction MDU started processing */
114 /** Last Division Operand of instruction MDU was processing */
115 uint32_t lastDivSize;
117 /** Last instruction name the MDU used */
118 std::string lastInstName;
120 /** Number of Instruction Requests the Resource Processes */
121 Stats::Scalar multInstReqsProcessed;
123 /** Number of Instruction Requests the Resource Processes */
124 Stats::Scalar divInstReqsProcessed;
129 class MDUEvent : public ResourceEvent
133 virtual ~MDUEvent() { }
136 virtual void process();
140 #endif //__CPU_INORDER_MULT_DIV_UNIT_HH__