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[gem5.git] / src / cpu / inorder / resources / mult_div_unit.hh
1 /*
2 * Copyright (c) 2007 MIPS Technologies, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Korey Sewell
29 *
30 */
31
32 #ifndef __CPU_INORDER_MULT_DIV_UNIT_HH__
33 #define __CPU_INORDER_MULT_DIV_UNIT_HH__
34
35 #include <vector>
36 #include <list>
37 #include <string>
38
39 #include "cpu/func_unit.hh"
40 #include "cpu/op_class.hh"
41 #include "cpu/inorder/first_stage.hh"
42 #include "cpu/inorder/resource.hh"
43 #include "cpu/inorder/inorder_dyn_inst.hh"
44
45 class MDUEvent;
46
47 class MultDivUnit : public Resource {
48 public:
49 typedef ThePipeline::DynInstPtr DynInstPtr;
50
51 enum Command {
52 StartMultDiv,
53 EndMultDiv,
54 MultDiv
55 };
56
57 public:
58 MultDivUnit(std::string res_name, int res_id, int res_width,
59 int res_latency, InOrderCPU *_cpu, ThePipeline::Params *params);
60
61 public:
62 /** Override default Resource getSlot(). Will only getSlot if
63 * valid mult/div sequence is being maintained
64 */
65 virtual int getSlot(DynInstPtr inst);
66
67 virtual int findSlot(DynInstPtr inst);
68
69 virtual void freeSlot(int slot_idx);
70
71 virtual void init();
72
73 /** Get Operand Size For A Division Operation */
74 int getDivOpSize(DynInstPtr inst);
75
76 /** Override default Resource execute */
77 virtual void execute(int slot_num);
78
79 void exeMulDiv(int slot_num);
80
81 /** Register extra resource stats */
82 virtual void regStats();
83
84 void requestAgain(DynInstPtr inst, bool &try_request);
85
86 protected:
87 /** Latency & Repeat Rate for Multiply Insts */
88 unsigned multRepeatRate;
89 unsigned multLatency;
90
91 /** Latency & Repeat Rate for 8-bit Divide Insts */
92 unsigned div8RepeatRate;
93 unsigned div8Latency;
94
95 /** Latency & Repeat Rate for 16-bit Divide Insts */
96 unsigned div16RepeatRate;
97 unsigned div16Latency;
98
99 /** Latency & Repeat Rate for 24-bit Divide Insts */
100 unsigned div24RepeatRate;
101 unsigned div24Latency;
102
103 /** Latency & Repeat Rate for 32-bit Divide Insts */
104 unsigned div32RepeatRate;
105 unsigned div32Latency;
106
107 /** Last cycle that MDU was used */
108 Tick lastMDUCycle;
109
110 /** Last type of instruction MDU started processing */
111 OpClass lastOpType;
112
113 /** Last Division Operand of instruction MDU was processing */
114 uint32_t lastDivSize;
115
116 /** Last instruction name the MDU used */
117 std::string lastInstName;
118
119 /** Number of Instruction Requests the Resource Processes */
120 Stats::Scalar multInstReqsProcessed;
121
122 /** Number of Instruction Requests the Resource Processes */
123 Stats::Scalar divInstReqsProcessed;
124
125 MDUEvent *mduEvent;
126 };
127
128 class MDUEvent : public ResourceEvent
129 {
130 public:
131 MDUEvent();
132 virtual ~MDUEvent() { }
133
134
135 virtual void process();
136 };
137
138
139 #endif //__CPU_INORDER_MULT_DIV_UNIT_HH__