src/cpu/inorder/resources/tlb_unit.cc

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #include <vector>
  33 #include <list>
  34 #include "arch/isa_traits.hh"
  35 #include "cpu/inorder/pipeline_traits.hh"
  36 #include "cpu/inorder/first_stage.hh"
  37 #include "cpu/inorder/resources/tlb_unit.hh"
  38 #include "cpu/inorder/cpu.hh"
  39
  40 using namespace std;
  41 using namespace TheISA;
  42 using namespace ThePipeline;
  43
  44 TLBUnit::TLBUnit(string res_name, int res_id, int res_width,
  45                  int res_latency, InOrderCPU *_cpu, ThePipeline::Params *params)
  46     : InstBuffer(res_name, res_id, res_width, res_latency, _cpu, params)
  47 {
  48     // Hard-Code Selection For Now
  49     if (res_name == "I-TLB")
  50         _tlb = params->itb;
  51     else if (res_name == "D-TLB")
  52         _tlb = params->dtb;
  53     else
  54         fatal("Unrecognized TLB name passed by user");
  55
  56     for (int i=0; i < MaxThreads; i++) {
  57         tlbBlocked[i] = false;
  58     }
  59 }
  60
  61 TheISA::TLB*
  62 TLBUnit::tlb()
  63 {
  64     return _tlb;
  65
  66 }
  67
  68 void
  69 TLBUnit::init()
  70 {
  71     resourceEvent = new TLBUnitEvent[width];
  72
  73     initSlots();
  74 }
  75
  76 int
  77 TLBUnit::getSlot(DynInstPtr inst)
  78 {
  79     if (tlbBlocked[inst->threadNumber]) {
  80         return -1;
  81     } else {
  82         return Resource::getSlot(inst);
  83     }
  84 }
  85
  86 ResourceRequest*
  87 TLBUnit::getRequest(DynInstPtr _inst, int stage_num,
  88                             int res_idx, int slot_num,
  89                             unsigned cmd)
  90 {
  91     return new TLBUnitRequest(this, _inst, stage_num, res_idx, slot_num,
  92                           cmd);
  93 }
  94
  95 void
  96 TLBUnit::execute(int slot_idx)
  97 {
  98     // After this is working, change this to a reinterpret cast
  99     // for performance considerations
 100     TLBUnitRequest* tlb_req = dynamic_cast<TLBUnitRequest*>(reqMap[slot_idx]);
 101     assert(tlb_req != 0x0);
 102
 103     DynInstPtr inst = tlb_req->inst;
 104     int tid, seq_num, stage_num;
 105
 106     tid = inst->readTid();
 107     seq_num = inst->seqNum;
 108     stage_num = tlb_req->getStageNum();
 109
 110     tlb_req->fault = NoFault;
 111
 112     assert(cpu->thread[tid]->getTC() != 0x0);
 113     assert(cpu->pipelineStage[stage_num] != 0x0);
 114
 115     switch (tlb_req->cmd)
 116     {
 117       case FetchLookup:
 118         {
 119             tlb_req->fault =
 120                 _tlb->translateAtomic(tlb_req->memReq,
 121                         cpu->thread[tid]->getTC(), false, true);
 122
 123             if (tlb_req->fault != NoFault) {
 124                 DPRINTF(InOrderTLB, "[tid:%i]: %s encountered while translating "
 125                         "addr:%08p for [sn:%i].\n", tid, tlb_req->fault->name(),
 126                         tlb_req->memReq->getVaddr(), seq_num);
 127                 //insert(inst);
 128                 cpu->pipelineStage[stage_num]->setResStall(tlb_req, tid);
 129                 tlbBlocked[tid] = true;
 130                 scheduleEvent(slot_idx, 1);
 131
 132                 // @TODO: SHOULDNT BREAK EXECUTION at misspeculated PC Fault
 133                 // Let CPU handle the fault
 134                 cpu->trap(tlb_req->fault, tid);
 135             } else {
 136                 DPRINTF(InOrderTLB, "[tid:%i]: [sn:%i] virt. addr %08p translated "
 137                         "to phys. addr:%08p.\n", tid, seq_num,
 138                         tlb_req->memReq->getVaddr(),
 139                         tlb_req->memReq->getPaddr());
 140                 tlb_req->done();
 141             }
 142         }
 143         break;
 144
 145       case DataLookup:
 146         {
 147             DPRINTF(InOrderTLB, "[tid:%i]: [sn:%i]: Attempting to translate %08p.\n",
 148                     tid, seq_num, tlb_req->memReq->getVaddr());
 149
 150             tlb_req->fault =
 151                 _tlb->translateAtomic(tlb_req->memReq,
 152                         cpu->thread[tid]->getTC());
 153
 154             if (tlb_req->fault != NoFault) {
 155                 DPRINTF(InOrderTLB, "[tid:%i]: %s encountered while translating "
 156                         "addr:%08p for [sn:%i].\n", tid, tlb_req->fault->name(),
 157                         tlb_req->memReq->getVaddr(), seq_num);
 158                 //insert(inst);
 159                 cpu->pipelineStage[stage_num]->setResStall(tlb_req, tid);
 160                 tlbBlocked[tid] = true;
 161                 scheduleEvent(slot_idx, 1);
 162
 163                 // Let CPU handle the fault
 164                 cpu->trap(tlb_req->fault, tid);
 165             } else {
 166                 DPRINTF(InOrderTLB, "[tid:%i]: [sn:%i] virt. addr %08p translated "
 167                         "to phys. addr:%08p.\n", tid, seq_num,
 168                         tlb_req->memReq->getVaddr(),
 169                         tlb_req->memReq->getPaddr());
 170                 tlb_req->done();
 171             }
 172         }
 173         break;
 174
 175       default:
 176         fatal("Unrecognized command to %s", resName);
 177     }
 178 }
 179
 180 TLBUnitEvent::TLBUnitEvent()
 181     : ResourceEvent()
 182 { }
 183
 184 void
 185 TLBUnitEvent::process()
 186 {
 187     DynInstPtr inst = resource->reqMap[slotIdx]->inst;
 188     int stage_num = resource->reqMap[slotIdx]->getStageNum();
 189     int tid = inst->threadNumber;
 190
 191     DPRINTF(InOrderTLB, "Waking up from TLB Miss caused by [sn:%i].\n",
 192             inst->seqNum);
 193
 194     TLBUnit* tlb_res = dynamic_cast<TLBUnit*>(resource);
 195     assert(tlb_res);
 196
 197     tlb_res->tlbBlocked[tid] = false;
 198
 199     tlb_res->cpu->pipelineStage[stage_num]->unsetResStall(resource->reqMap[slotIdx], tid);
 200
 201     // Effectively NOP the instruction but still allow it
 202     // to commit
 203     //while (!inst->resSched.empty() &&
 204     //   inst->resSched.top()->stageNum != ThePipeline::NumStages - 1) {
 205     //inst->resSched.pop();
 206     //}
 207 }