2 * Copyright (c) 2007 MIPS Technologies, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Korey Sewell
35 #include "arch/isa_traits.hh"
36 #include "config/the_isa.hh"
37 #include "cpu/inorder/resources/tlb_unit.hh"
38 #include "cpu/inorder/cpu.hh"
39 #include "cpu/inorder/first_stage.hh"
40 #include "cpu/inorder/pipeline_traits.hh"
43 using namespace TheISA
;
44 using namespace ThePipeline
;
46 TLBUnit::TLBUnit(string res_name
, int res_id
, int res_width
,
47 int res_latency
, InOrderCPU
*_cpu
, ThePipeline::Params
*params
)
48 : Resource(res_name
, res_id
, res_width
, res_latency
, _cpu
)
50 // Hard-Code Selection For Now
51 if (res_name
== "I-TLB")
53 else if (res_name
== "D-TLB")
56 fatal("Unrecognized TLB name passed by user");
58 for (int i
=0; i
< MaxThreads
; i
++) {
59 tlbBlocked
[i
] = false;
73 resourceEvent
= new TLBUnitEvent
[width
];
75 for (int i
= 0; i
< width
; i
++) {
76 reqs
[i
] = new TLBUnitRequest(this);
83 TLBUnit::getSlot(DynInstPtr inst
)
85 if (tlbBlocked
[inst
->threadNumber
]) {
88 return Resource::getSlot(inst
);
93 TLBUnit::getRequest(DynInstPtr _inst
, int stage_num
,
94 int res_idx
, int slot_num
,
97 TLBUnitRequest
*tlb_req
= dynamic_cast<TLBUnitRequest
*>(reqs
[slot_num
]);
98 tlb_req
->setRequest(inst
, stage_num
, id
, slot_num
, cmd
);
103 TLBUnit::execute(int slot_idx
)
105 // After this is working, change this to a reinterpret cast
106 // for performance considerations
107 TLBUnitRequest
* tlb_req
= dynamic_cast<TLBUnitRequest
*>(reqs
[slot_idx
]);
108 assert(tlb_req
!= 0x0);
110 DynInstPtr inst
= tlb_req
->inst
;
111 ThreadID tid
= inst
->readTid();
112 InstSeqNum seq_num
= inst
->seqNum
;
113 int stage_num
= tlb_req
->getStageNum();
115 tlb_req
->fault
= NoFault
;
117 assert(cpu
->thread
[tid
]->getTC() != 0x0);
118 assert(cpu
->pipelineStage
[stage_num
] != 0x0);
120 switch (tlb_req
->cmd
)
125 _tlb
->translateAtomic(tlb_req
->memReq
,
126 cpu
->thread
[tid
]->getTC(), TheISA::TLB::Execute
);
128 if (tlb_req
->fault
!= NoFault
) {
129 DPRINTF(InOrderTLB
, "[tid:%i]: %s encountered while translating "
130 "addr:%08p for [sn:%i].\n", tid
, tlb_req
->fault
->name(),
131 tlb_req
->memReq
->getVaddr(), seq_num
);
133 DPRINTF(InOrderTLB
, "slot:%i sn:%i schedule event.\n", slot_idx
, seq_num
);
135 cpu
->pipelineStage
[stage_num
]->setResStall(tlb_req
, tid
);
136 tlbBlocked
[tid
] = true;
137 scheduleEvent(slot_idx
, 1);
139 // @TODO: SHOULDNT BREAK EXECUTION at misspeculated PC Fault
140 // Let CPU handle the fault
141 cpu
->trap(tlb_req
->fault
, tid
);
143 DPRINTF(InOrderTLB
, "[tid:%i]: [sn:%i] virt. addr %08p translated "
144 "to phys. addr:%08p.\n", tid
, seq_num
,
145 tlb_req
->memReq
->getVaddr(),
146 tlb_req
->memReq
->getPaddr());
153 case DataWriteLookup
:
155 DPRINTF(InOrderTLB
, "[tid:%i]: [sn:%i]: Attempting to translate %08p.\n",
156 tid
, seq_num
, tlb_req
->memReq
->getVaddr());
159 TheISA::TLB::Mode tlb_mode
= (tlb_req
->cmd
== DataReadLookup
) ?
160 TheISA::TLB::Read
: TheISA::TLB::Write
;
163 _tlb
->translateAtomic(tlb_req
->memReq
,
164 cpu
->thread
[tid
]->getTC(), tlb_mode
);
166 if (tlb_req
->fault
!= NoFault
) {
167 DPRINTF(InOrderTLB
, "[tid:%i]: %s encountered while translating "
168 "addr:%08p for [sn:%i] %s.\n", tid
, tlb_req
->fault
->name(),
169 tlb_req
->memReq
->getVaddr(), seq_num
, inst
->instName());
171 if (inst
->isDataPrefetch()) {
172 DPRINTF(InOrderTLB
, "Ignoring %s fault for data prefetch\n",
173 tlb_req
->fault
->name());
175 tlb_req
->fault
= NoFault
;
179 cpu
->pipelineStage
[stage_num
]->setResStall(tlb_req
, tid
);
180 tlbBlocked
[tid
] = true;
181 scheduleEvent(slot_idx
, 1);
183 // Let CPU handle the fault
184 cpu
->trap(tlb_req
->fault
, tid
, inst
);
187 DPRINTF(InOrderTLB
, "[tid:%i]: [sn:%i] virt. addr %08p translated "
188 "to phys. addr:%08p.\n", tid
, seq_num
,
189 tlb_req
->memReq
->getVaddr(),
190 tlb_req
->memReq
->getPaddr());
197 fatal("Unrecognized command to %s", resName
);
201 TLBUnitEvent::TLBUnitEvent()
206 TLBUnitEvent::process()
208 DynInstPtr inst
= resource
->reqs
[slotIdx
]->inst
;
209 int stage_num
= resource
->reqs
[slotIdx
]->getStageNum();
210 ThreadID tid
= inst
->threadNumber
;
212 DPRINTF(InOrderTLB
, "Waking up from TLB Miss caused by [sn:%i].\n",
215 TLBUnit
* tlb_res
= dynamic_cast<TLBUnit
*>(resource
);
218 tlb_res
->tlbBlocked
[tid
] = false;
220 tlb_res
->cpu
->pipelineStage
[stage_num
]->
221 unsetResStall(tlb_res
->reqs
[slotIdx
], tid
);
225 TLBUnit::squash(DynInstPtr inst
, int stage_num
,
226 InstSeqNum squash_seq_num
, ThreadID tid
)
228 for (int i
= 0; i
< width
; i
++) {
229 ResReqPtr req_ptr
= reqs
[i
];
231 if (req_ptr
->valid
&&
232 req_ptr
->getInst()->readTid() == tid
&&
233 req_ptr
->getInst()->seqNum
> squash_seq_num
) {
235 DPRINTF(Resource
, "[tid:%i]: Squashing [sn:%i].\n",
236 req_ptr
->getInst()->readTid(),
237 req_ptr
->getInst()->seqNum
);
239 req_ptr
->setSquashed();
241 int req_slot_num
= req_ptr
->getSlot();
243 tlbBlocked
[tid
] = false;
245 int stall_stage
= reqs
[req_slot_num
]->getStageNum();
247 cpu
->pipelineStage
[stall_stage
]->
248 unsetResStall(reqs
[req_slot_num
], tid
);
250 if (resourceEvent
[req_slot_num
].scheduled())
251 unscheduleEvent(req_slot_num
);
253 freeSlot(req_slot_num
);