2 * Copyright (c) 2007 MIPS Technologies, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Korey Sewell
34 #include "arch/isa_traits.hh"
35 #include "cpu/inorder/pipeline_traits.hh"
36 #include "cpu/inorder/first_stage.hh"
37 #include "cpu/inorder/resources/tlb_unit.hh"
38 #include "cpu/inorder/cpu.hh"
41 using namespace TheISA
;
42 using namespace ThePipeline
;
44 TLBUnit::TLBUnit(string res_name
, int res_id
, int res_width
,
45 int res_latency
, InOrderCPU
*_cpu
, ThePipeline::Params
*params
)
46 : Resource(res_name
, res_id
, res_width
, res_latency
, _cpu
)
48 // Hard-Code Selection For Now
49 if (res_name
== "I-TLB")
51 else if (res_name
== "D-TLB")
54 fatal("Unrecognized TLB name passed by user");
56 for (int i
=0; i
< MaxThreads
; i
++) {
57 tlbBlocked
[i
] = false;
71 resourceEvent
= new TLBUnitEvent
[width
];
77 TLBUnit::getSlot(DynInstPtr inst
)
79 if (tlbBlocked
[inst
->threadNumber
]) {
82 return Resource::getSlot(inst
);
87 TLBUnit::getRequest(DynInstPtr _inst
, int stage_num
,
88 int res_idx
, int slot_num
,
91 return new TLBUnitRequest(this, _inst
, stage_num
, res_idx
, slot_num
,
96 TLBUnit::execute(int slot_idx
)
98 // After this is working, change this to a reinterpret cast
99 // for performance considerations
100 TLBUnitRequest
* tlb_req
= dynamic_cast<TLBUnitRequest
*>(reqMap
[slot_idx
]);
101 assert(tlb_req
!= 0x0);
103 DynInstPtr inst
= tlb_req
->inst
;
104 ThreadID tid
= inst
->readTid();
105 int seq_num
= inst
->seqNum
;
106 int stage_num
= tlb_req
->getStageNum();
108 tlb_req
->fault
= NoFault
;
110 assert(cpu
->thread
[tid
]->getTC() != 0x0);
111 assert(cpu
->pipelineStage
[stage_num
] != 0x0);
113 switch (tlb_req
->cmd
)
118 _tlb
->translateAtomic(tlb_req
->memReq
,
119 cpu
->thread
[tid
]->getTC(), TheISA::TLB::Execute
);
121 if (tlb_req
->fault
!= NoFault
) {
122 DPRINTF(InOrderTLB
, "[tid:%i]: %s encountered while translating "
123 "addr:%08p for [sn:%i].\n", tid
, tlb_req
->fault
->name(),
124 tlb_req
->memReq
->getVaddr(), seq_num
);
126 DPRINTF(InOrderTLB
, "slot:%i sn:%i schedule event.\n", slot_idx
, seq_num
);
128 cpu
->pipelineStage
[stage_num
]->setResStall(tlb_req
, tid
);
129 tlbBlocked
[tid
] = true;
130 scheduleEvent(slot_idx
, 1);
132 // @TODO: SHOULDNT BREAK EXECUTION at misspeculated PC Fault
133 // Let CPU handle the fault
134 cpu
->trap(tlb_req
->fault
, tid
);
136 DPRINTF(InOrderTLB
, "[tid:%i]: [sn:%i] virt. addr %08p translated "
137 "to phys. addr:%08p.\n", tid
, seq_num
,
138 tlb_req
->memReq
->getVaddr(),
139 tlb_req
->memReq
->getPaddr());
146 case DataWriteLookup
:
148 DPRINTF(InOrderTLB
, "[tid:%i]: [sn:%i]: Attempting to translate %08p.\n",
149 tid
, seq_num
, tlb_req
->memReq
->getVaddr());
152 TheISA::TLB::Mode tlb_mode
= (tlb_req
->cmd
== DataReadLookup
) ?
153 TheISA::TLB::Read
: TheISA::TLB::Write
;
156 _tlb
->translateAtomic(tlb_req
->memReq
,
157 cpu
->thread
[tid
]->getTC(), tlb_mode
);
159 if (tlb_req
->fault
!= NoFault
) {
160 DPRINTF(InOrderTLB
, "[tid:%i]: %s encountered while translating "
161 "addr:%08p for [sn:%i] %s.\n", tid
, tlb_req
->fault
->name(),
162 tlb_req
->memReq
->getVaddr(), seq_num
, inst
->instName());
164 if (inst
->isDataPrefetch()) {
165 DPRINTF(InOrderTLB
, "Ignoring %s fault for data prefetch\n",
166 tlb_req
->fault
->name());
168 tlb_req
->fault
= NoFault
;
172 cpu
->pipelineStage
[stage_num
]->setResStall(tlb_req
, tid
);
173 tlbBlocked
[tid
] = true;
174 scheduleEvent(slot_idx
, 1);
176 // Let CPU handle the fault
177 cpu
->trap(tlb_req
->fault
, tid
);
180 DPRINTF(InOrderTLB
, "[tid:%i]: [sn:%i] virt. addr %08p translated "
181 "to phys. addr:%08p.\n", tid
, seq_num
,
182 tlb_req
->memReq
->getVaddr(),
183 tlb_req
->memReq
->getPaddr());
190 fatal("Unrecognized command to %s", resName
);
194 TLBUnitEvent::TLBUnitEvent()
199 TLBUnitEvent::process()
201 DynInstPtr inst
= resource
->reqMap
[slotIdx
]->inst
;
202 int stage_num
= resource
->reqMap
[slotIdx
]->getStageNum();
203 ThreadID tid
= inst
->threadNumber
;
205 DPRINTF(InOrderTLB
, "Waking up from TLB Miss caused by [sn:%i].\n",
208 TLBUnit
* tlb_res
= dynamic_cast<TLBUnit
*>(resource
);
211 tlb_res
->tlbBlocked
[tid
] = false;
213 tlb_res
->cpu
->pipelineStage
[stage_num
]->unsetResStall(tlb_res
->reqMap
[slotIdx
], tid
);
215 // Effectively NOP the instruction but still allow it
217 //while (!inst->resSched.empty() &&
218 // inst->resSched.top()->stageNum != ThePipeline::NumStages - 1) {
219 //inst->resSched.pop();
224 TLBUnit::squash(DynInstPtr inst
, int stage_num
,
225 InstSeqNum squash_seq_num
, ThreadID tid
)
227 //@TODO: Figure out a way to consolidate common parts
228 // of this squash code
229 std::vector
<int> slot_remove_list
;
231 map
<int, ResReqPtr
>::iterator map_it
= reqMap
.begin();
232 map
<int, ResReqPtr
>::iterator map_end
= reqMap
.end();
234 while (map_it
!= map_end
) {
235 ResReqPtr req_ptr
= (*map_it
).second
;
238 req_ptr
->getInst()->readTid() == tid
&&
239 req_ptr
->getInst()->seqNum
> squash_seq_num
) {
241 DPRINTF(Resource
, "[tid:%i]: Squashing [sn:%i].\n",
242 req_ptr
->getInst()->readTid(),
243 req_ptr
->getInst()->seqNum
);
245 req_ptr
->setSquashed();
247 int req_slot_num
= req_ptr
->getSlot();
249 tlbBlocked
[tid
] = false;
251 int stall_stage
= reqMap
[req_slot_num
]->getStageNum();
253 cpu
->pipelineStage
[stall_stage
]->unsetResStall(reqMap
[req_slot_num
], tid
);
255 if (resourceEvent
[req_slot_num
].scheduled())
256 unscheduleEvent(req_slot_num
);
258 // Mark request for later removal
259 cpu
->reqRemoveList
.push(req_ptr
);
261 // Mark slot for removal from resource
262 slot_remove_list
.push_back(req_ptr
->getSlot());
268 // Now Delete Slot Entry from Req. Map
269 for (int i
= 0; i
< slot_remove_list
.size(); i
++) {
270 freeSlot(slot_remove_list
[i
]);