src/cpu/inorder/resources/tlb_unit.cc

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #include <vector>
  33 #include <list>
  34 #include "arch/isa_traits.hh"
  35 #include "cpu/inorder/pipeline_traits.hh"
  36 #include "cpu/inorder/resources/tlb_unit.hh"
  37 #include "cpu/inorder/cpu.hh"
  38
  39 using namespace std;
  40 using namespace TheISA;
  41 using namespace ThePipeline;
  42
  43 TLBUnit::TLBUnit(string res_name, int res_id, int res_width,
  44                  int res_latency, InOrderCPU *_cpu, ThePipeline::Params *params)
  45     : InstBuffer(res_name, res_id, res_width, res_latency, _cpu, params)
  46 {
  47     for (int i=0; i < MaxThreads; i++) {
  48         tlbBlocked[i] = false;
  49     }
  50 }
  51
  52 void
  53 TLBUnit::init()
  54 {
  55     resourceEvent = new TLBUnitEvent[width];
  56
  57     initSlots();
  58 }
  59
  60 int
  61 TLBUnit::getSlot(DynInstPtr inst)
  62 {
  63     if (tlbBlocked[inst->threadNumber]) {
  64         return -1;
  65     } else {
  66         return Resource::getSlot(inst);
  67     }
  68 }
  69
  70 ResourceRequest*
  71 TLBUnit::getRequest(DynInstPtr _inst, int stage_num,
  72                             int res_idx, int slot_num,
  73                             unsigned cmd)
  74 {
  75     return new TLBUnitRequest(this, _inst, stage_num, res_idx, slot_num,
  76                           cmd);
  77 }
  78
  79 void
  80 TLBUnit::execute(int slot_idx)
  81 {
  82     // After this is working, change this to a reinterpret cast
  83     // for performance considerations
  84     TLBUnitRequest* tlb_req = dynamic_cast<TLBUnitRequest*>(reqMap[slot_idx]);
  85     assert(tlb_req);
  86
  87     DynInstPtr inst = tlb_req->inst;
  88     int tid, seq_num, stage_num;
  89
  90     tid = inst->readTid();
  91     seq_num = inst->seqNum;
  92     stage_num = tlb_req->getStageNum();
  93
  94     tlb_req->fault = NoFault;
  95
  96     switch (tlb_req->cmd)
  97     {
  98       case FetchLookup:
  99         {
 100             tlb_req->fault =
 101                 this->cpu->itb->translateAtomic(tlb_req->memReq,
 102                         cpu->thread[tid]->getTC());
 103
 104             if (tlb_req->fault != NoFault) {
 105                 DPRINTF(Resource, "[tid:%i]: %s encountered while translating "
 106                         "addr:%08p for [sn:%i].\n", tid, tlb_req->fault->name(),
 107                         tlb_req->memReq->getVaddr(), seq_num);
 108                 //insert(inst);
 109                 cpu->pipelineStage[stage_num]->setResStall(tlb_req, tid);
 110                 tlbBlocked[tid] = true;
 111                 scheduleEvent(slot_idx, 1);
 112
 113                 // @TODO: SHOULDNT BREAK EXECUTION at misspeculated PC Fault
 114                 // Let CPU handle the fault
 115                 cpu->trap(tlb_req->fault, tid);
 116             } else {
 117                 DPRINTF(Resource, "[tid:%i]: [sn:%i] virt. addr %08p translated "
 118                         "to phys. addr:%08p.\n", tid, seq_num,
 119                         tlb_req->memReq->getVaddr(),
 120                         tlb_req->memReq->getPaddr());
 121                 tlb_req->done();
 122             }
 123         }
 124         break;
 125
 126       case DataLookup:
 127         {
 128             DPRINTF(Resource, "[tid:%i]: [sn:%i]: Attempting to translate %08p.\n",
 129                     tid, seq_num, tlb_req->memReq->getVaddr());
 130
 131             tlb_req->fault =
 132                 this->cpu->itb->translateAtomic(tlb_req->memReq,
 133                         cpu->thread[tid]->getTC());
 134
 135             if (tlb_req->fault != NoFault) {
 136                 DPRINTF(Resource, "[tid:%i]: %s encountered while translating "
 137                         "addr:%08p for [sn:%i].\n", tid, tlb_req->fault->name(),
 138                         tlb_req->memReq->getVaddr(), seq_num);
 139                 //insert(inst);
 140                 cpu->pipelineStage[stage_num]->setResStall(tlb_req, tid);
 141                 tlbBlocked[tid] = true;
 142                 scheduleEvent(slot_idx, 1);
 143
 144                 // Let CPU handle the fault
 145                 cpu->trap(tlb_req->fault, tid);
 146             } else {
 147                 DPRINTF(Resource, "[tid:%i]: [sn:%i] virt. addr %08p translated "
 148                         "to phys. addr:%08p.\n", tid, seq_num,
 149                         tlb_req->memReq->getVaddr(),
 150                         tlb_req->memReq->getPaddr());
 151                 tlb_req->done();
 152             }
 153         }
 154         break;
 155
 156       default:
 157         fatal("Unrecognized command to %s", resName);
 158     }
 159 }
 160
 161 TLBUnitEvent::TLBUnitEvent()
 162     : ResourceEvent()
 163 { }
 164
 165 void
 166 TLBUnitEvent::process()
 167 {
 168     DynInstPtr inst = resource->reqMap[slotIdx]->inst;
 169     int stage_num = resource->reqMap[slotIdx]->getStageNum();
 170     int tid = inst->threadNumber;
 171
 172     DPRINTF(Resource, "Waking up from TLB Miss caused by [sn:%i].\n",
 173             inst->seqNum);
 174
 175     TLBUnit* tlb_res = dynamic_cast<TLBUnit*>(resource);
 176     assert(tlb_res);
 177
 178     tlb_res->tlbBlocked[tid] = false;
 179
 180     tlb_res->cpu->pipelineStage[stage_num]->unsetResStall(resource->reqMap[slotIdx], tid);
 181
 182     // Effectively NOP the instruction but still allow it
 183     // to commit
 184     //while (!inst->resSched.empty() &&
 185     //   inst->resSched.top()->stageNum != ThePipeline::NumStages - 1) {
 186     //inst->resSched.pop();
 187     //}
 188 }