2 * Copyright (c) 2007 MIPS Technologies, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Korey Sewell
35 #include "arch/isa_traits.hh"
36 #include "config/the_isa.hh"
37 #include "cpu/inorder/pipeline_traits.hh"
38 #include "cpu/inorder/first_stage.hh"
39 #include "cpu/inorder/resources/tlb_unit.hh"
40 #include "cpu/inorder/cpu.hh"
43 using namespace TheISA
;
44 using namespace ThePipeline
;
46 TLBUnit::TLBUnit(string res_name
, int res_id
, int res_width
,
47 int res_latency
, InOrderCPU
*_cpu
, ThePipeline::Params
*params
)
48 : Resource(res_name
, res_id
, res_width
, res_latency
, _cpu
)
50 // Hard-Code Selection For Now
51 if (res_name
== "I-TLB")
53 else if (res_name
== "D-TLB")
56 fatal("Unrecognized TLB name passed by user");
58 for (int i
=0; i
< MaxThreads
; i
++) {
59 tlbBlocked
[i
] = false;
73 resourceEvent
= new TLBUnitEvent
[width
];
79 TLBUnit::getSlot(DynInstPtr inst
)
81 if (tlbBlocked
[inst
->threadNumber
]) {
84 return Resource::getSlot(inst
);
89 TLBUnit::getRequest(DynInstPtr _inst
, int stage_num
,
90 int res_idx
, int slot_num
,
93 return new TLBUnitRequest(this, _inst
, stage_num
, res_idx
, slot_num
,
98 TLBUnit::execute(int slot_idx
)
100 // After this is working, change this to a reinterpret cast
101 // for performance considerations
102 TLBUnitRequest
* tlb_req
= dynamic_cast<TLBUnitRequest
*>(reqMap
[slot_idx
]);
103 assert(tlb_req
!= 0x0);
105 DynInstPtr inst
= tlb_req
->inst
;
106 ThreadID tid
= inst
->readTid();
107 int seq_num
= inst
->seqNum
;
108 int stage_num
= tlb_req
->getStageNum();
110 tlb_req
->fault
= NoFault
;
112 assert(cpu
->thread
[tid
]->getTC() != 0x0);
113 assert(cpu
->pipelineStage
[stage_num
] != 0x0);
115 switch (tlb_req
->cmd
)
120 _tlb
->translateAtomic(tlb_req
->memReq
,
121 cpu
->thread
[tid
]->getTC(), TheISA::TLB::Execute
);
123 if (tlb_req
->fault
!= NoFault
) {
124 DPRINTF(InOrderTLB
, "[tid:%i]: %s encountered while translating "
125 "addr:%08p for [sn:%i].\n", tid
, tlb_req
->fault
->name(),
126 tlb_req
->memReq
->getVaddr(), seq_num
);
128 DPRINTF(InOrderTLB
, "slot:%i sn:%i schedule event.\n", slot_idx
, seq_num
);
130 cpu
->pipelineStage
[stage_num
]->setResStall(tlb_req
, tid
);
131 tlbBlocked
[tid
] = true;
132 scheduleEvent(slot_idx
, 1);
134 // @TODO: SHOULDNT BREAK EXECUTION at misspeculated PC Fault
135 // Let CPU handle the fault
136 cpu
->trap(tlb_req
->fault
, tid
);
138 DPRINTF(InOrderTLB
, "[tid:%i]: [sn:%i] virt. addr %08p translated "
139 "to phys. addr:%08p.\n", tid
, seq_num
,
140 tlb_req
->memReq
->getVaddr(),
141 tlb_req
->memReq
->getPaddr());
148 case DataWriteLookup
:
150 DPRINTF(InOrderTLB
, "[tid:%i]: [sn:%i]: Attempting to translate %08p.\n",
151 tid
, seq_num
, tlb_req
->memReq
->getVaddr());
154 TheISA::TLB::Mode tlb_mode
= (tlb_req
->cmd
== DataReadLookup
) ?
155 TheISA::TLB::Read
: TheISA::TLB::Write
;
158 _tlb
->translateAtomic(tlb_req
->memReq
,
159 cpu
->thread
[tid
]->getTC(), tlb_mode
);
161 if (tlb_req
->fault
!= NoFault
) {
162 DPRINTF(InOrderTLB
, "[tid:%i]: %s encountered while translating "
163 "addr:%08p for [sn:%i] %s.\n", tid
, tlb_req
->fault
->name(),
164 tlb_req
->memReq
->getVaddr(), seq_num
, inst
->instName());
166 if (inst
->isDataPrefetch()) {
167 DPRINTF(InOrderTLB
, "Ignoring %s fault for data prefetch\n",
168 tlb_req
->fault
->name());
170 tlb_req
->fault
= NoFault
;
174 cpu
->pipelineStage
[stage_num
]->setResStall(tlb_req
, tid
);
175 tlbBlocked
[tid
] = true;
176 scheduleEvent(slot_idx
, 1);
178 // Let CPU handle the fault
179 cpu
->trap(tlb_req
->fault
, tid
, inst
);
182 DPRINTF(InOrderTLB
, "[tid:%i]: [sn:%i] virt. addr %08p translated "
183 "to phys. addr:%08p.\n", tid
, seq_num
,
184 tlb_req
->memReq
->getVaddr(),
185 tlb_req
->memReq
->getPaddr());
192 fatal("Unrecognized command to %s", resName
);
196 TLBUnitEvent::TLBUnitEvent()
201 TLBUnitEvent::process()
203 DynInstPtr inst
= resource
->reqMap
[slotIdx
]->inst
;
204 int stage_num
= resource
->reqMap
[slotIdx
]->getStageNum();
205 ThreadID tid
= inst
->threadNumber
;
207 DPRINTF(InOrderTLB
, "Waking up from TLB Miss caused by [sn:%i].\n",
210 TLBUnit
* tlb_res
= dynamic_cast<TLBUnit
*>(resource
);
213 tlb_res
->tlbBlocked
[tid
] = false;
215 tlb_res
->cpu
->pipelineStage
[stage_num
]->unsetResStall(tlb_res
->reqMap
[slotIdx
], tid
);
217 // Effectively NOP the instruction but still allow it
219 //while (!inst->resSched.empty() &&
220 // inst->resSched.top()->stageNum != ThePipeline::NumStages - 1) {
221 //inst->resSched.pop();
226 TLBUnit::squash(DynInstPtr inst
, int stage_num
,
227 InstSeqNum squash_seq_num
, ThreadID tid
)
229 //@TODO: Figure out a way to consolidate common parts
230 // of this squash code
231 std::vector
<int> slot_remove_list
;
233 map
<int, ResReqPtr
>::iterator map_it
= reqMap
.begin();
234 map
<int, ResReqPtr
>::iterator map_end
= reqMap
.end();
236 while (map_it
!= map_end
) {
237 ResReqPtr req_ptr
= (*map_it
).second
;
240 req_ptr
->getInst()->readTid() == tid
&&
241 req_ptr
->getInst()->seqNum
> squash_seq_num
) {
243 DPRINTF(Resource
, "[tid:%i]: Squashing [sn:%i].\n",
244 req_ptr
->getInst()->readTid(),
245 req_ptr
->getInst()->seqNum
);
247 req_ptr
->setSquashed();
249 int req_slot_num
= req_ptr
->getSlot();
251 tlbBlocked
[tid
] = false;
253 int stall_stage
= reqMap
[req_slot_num
]->getStageNum();
255 cpu
->pipelineStage
[stall_stage
]->unsetResStall(reqMap
[req_slot_num
], tid
);
257 if (resourceEvent
[req_slot_num
].scheduled())
258 unscheduleEvent(req_slot_num
);
260 // Mark request for later removal
261 cpu
->reqRemoveList
.push(req_ptr
);
263 // Mark slot for removal from resource
264 slot_remove_list
.push_back(req_ptr
->getSlot());
270 // Now Delete Slot Entry from Req. Map
271 for (int i
= 0; i
< slot_remove_list
.size(); i
++) {
272 freeSlot(slot_remove_list
[i
]);