src/cpu/inorder/resources/tlb_unit.hh

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #ifndef __CPU_INORDER_TLB_UNIT_HH__
  33 #define __CPU_INORDER_TLB_UNIT_HH__
  34
  35 #include <list>
  36 #include <string>
  37 #include <vector>
  38
  39 #include "config/the_isa.hh"
  40 #include "cpu/inorder/resources/inst_buffer.hh"
  41 #include "cpu/inorder/cpu.hh"
  42 #include "cpu/inorder/inorder_dyn_inst.hh"
  43 #include "cpu/inorder/pipeline_traits.hh"
  44
  45 class TLBUnit : public Resource
  46 {
  47   public:
  48     typedef ThePipeline::DynInstPtr DynInstPtr;
  49
  50     enum TLBCommand {
  51         FetchLookup,
  52         DataReadLookup,
  53         DataWriteLookup
  54     };
  55
  56   public:
  57     TLBUnit(std::string res_name, int res_id, int res_width,
  58               int res_latency, InOrderCPU *_cpu, ThePipeline::Params *params);
  59     virtual ~TLBUnit() {}
  60
  61     void init();
  62
  63     int getSlot(DynInstPtr inst);
  64
  65     virtual ResourceRequest* getRequest(DynInstPtr _inst, int stage_num,
  66                                         int res_idx, int slot_num,
  67                                         unsigned cmd);
  68
  69     virtual void execute(int slot_num);
  70
  71     void squash(DynInstPtr inst, int stage_num, InstSeqNum squash_seq_num,
  72                 ThreadID tid);
  73
  74     bool tlbBlocked[ThePipeline::MaxThreads];
  75
  76     TheISA::TLB* tlb();
  77
  78   protected:
  79     /** List of instructions this resource is currently
  80      *  processing.
  81      */
  82     std::list<DynInstPtr> instList;
  83
  84     TheISA::TLB *_tlb;
  85 };
  86
  87 class TLBUnitEvent : public ResourceEvent {
  88   public:
  89     /** Constructs a resource event. */
  90     TLBUnitEvent();
  91     virtual ~TLBUnitEvent() {}
  92
  93     /** Processes a resource event. */
  94     virtual void process();
  95 };
  96
  97 class TLBUnitRequest : public ResourceRequest {
  98   public:
  99     typedef ThePipeline::DynInstPtr DynInstPtr;
 100
 101   public:
 102     TLBUnitRequest(TLBUnit *res)
 103         : ResourceRequest(res), memReq(NULL)
 104     {
 105     }
 106
 107     RequestPtr memReq;
 108
 109     void setRequest(DynInstPtr inst, int stage_num, int res_idx, int slot_num,
 110                     unsigned _cmd)
 111     {
 112         Addr aligned_addr;
 113         int req_size;
 114         unsigned flags;
 115
 116         if (_cmd == TLBUnit::FetchLookup) {
 117             aligned_addr = inst->getMemAddr();
 118             req_size = sizeof(TheISA::MachInst);
 119             flags = 0;
 120             inst->fetchMemReq = new Request(inst->readTid(), aligned_addr,
 121                                             req_size, flags, inst->instAddr(),
 122                                             res->cpu->readCpuId(),
 123                                             inst->readTid());
 124             memReq = inst->fetchMemReq;
 125         } else {
 126             aligned_addr = inst->getMemAddr();;
 127             req_size = 0; //inst->getMemAccSize();
 128             flags = 0; //inst->getMemFlags();
 129
 130             if (req_size == 0 && (inst->isDataPrefetch() || inst->isInstPrefetch())) {
 131                 req_size = 8;
 132             }
 133
 134             inst->dataMemReq = new Request(inst->readTid(), aligned_addr,
 135                                            req_size, flags, inst->instAddr(),
 136                                            res->cpu->readCpuId(),
 137                                            inst->readTid());
 138             memReq = inst->dataMemReq;
 139         }
 140
 141         ResourceRequest::setRequest(inst, stage_num, res_idx, slot_num, _cmd);
 142     }
 143
 144 };
 145
 146
 147 #endif //__CPU_INORDER_TLB_UNIT_HH__