src/cpu/inorder/resources/use_def.hh

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #ifndef __CPU_INORDER_USE_DEF_UNIT_HH__
  33 #define __CPU_INORDER_USE_DEF_UNIT_HH__
  34
  35 #include <list>
  36 #include <string>
  37 #include <vector>
  38
  39 #include "cpu/inorder/first_stage.hh"
  40 #include "cpu/inorder/inorder_dyn_inst.hh"
  41 #include "cpu/inorder/pipeline_traits.hh"
  42 #include "cpu/inorder/reg_dep_map.hh"
  43 #include "cpu/inorder/resource.hh"
  44 #include "cpu/func_unit.hh"
  45
  46 class UseDefUnit : public Resource {
  47   public:
  48     typedef ThePipeline::DynInstPtr DynInstPtr;
  49     typedef TheISA::RegIndex RegIndex;
  50
  51     enum Command {
  52         ReadSrcReg,
  53         WriteDestReg,
  54         MarkDestRegs
  55     };
  56
  57   public:
  58     UseDefUnit(std::string res_name, int res_id, int res_width,
  59                int res_latency, InOrderCPU *_cpu, ThePipeline::Params *params);
  60
  61     void init();
  62
  63     ResourceRequest* getRequest(DynInstPtr _inst, int stage_num,
  64                                         int res_idx, int slot_num,
  65                                         unsigned cmd);
  66
  67     ResReqPtr findRequest(DynInstPtr inst);
  68
  69     void execute(int slot_num);
  70
  71     void updateAfterContextSwitch(DynInstPtr inst, ThreadID tid);
  72
  73     void regStats();
  74
  75   protected:
  76     RegDepMap *regDepMap[ThePipeline::MaxThreads];
  77
  78     bool *nonSpecInstActive[ThePipeline::MaxThreads];
  79     InstSeqNum *nonSpecSeqNum[ThePipeline::MaxThreads];
  80
  81     bool serializeOnNextInst[ThePipeline::MaxThreads];
  82     InstSeqNum serializeAfterSeqNum[ThePipeline::MaxThreads];
  83
  84     Stats::Average uniqueRegsPerSwitch;
  85     std::map<RegIndex, bool> uniqueIntRegMap;
  86     std::map<RegIndex, bool> uniqueFloatRegMap;
  87     std::map<RegIndex, bool> uniqueMiscRegMap;
  88
  89   public:
  90     class UseDefRequest : public ResourceRequest {
  91       public:
  92         typedef ThePipeline::DynInstPtr DynInstPtr;
  93
  94       public:
  95         UseDefRequest(UseDefUnit *res)
  96             : ResourceRequest(res)
  97         { }
  98
  99         int useDefIdx;
 100
 101         void setRequest(DynInstPtr _inst, int stage_num, int res_idx,
 102                         int slot_num, unsigned _cmd, int idx)
 103         {
 104             useDefIdx = idx;
 105
 106             ResourceRequest::setRequest(_inst, stage_num, res_idx, slot_num,
 107                                         _cmd);
 108         }
 109     };
 110
 111   protected:
 112     /** Int. Register File Reads */
 113     Stats::Scalar intRegFileReads;
 114
 115     /** Int. Register File Writes */
 116     Stats::Scalar intRegFileWrites;
 117
 118     /** Int. Register File Total Accesses (Read+Write) */
 119     Stats::Formula intRegFileAccs;
 120
 121     /** Float Register File Reads */
 122     Stats::Scalar floatRegFileReads;
 123
 124     /** Float Register File Writes */
 125     Stats::Scalar floatRegFileWrites;
 126
 127     /** Float Register File Total Accesses (Read+Write) */
 128     Stats::Formula floatRegFileAccs;
 129
 130     /** Source Register Forwarding */
 131     Stats::Scalar regForwards;
 132 };
 133
 134 #endif //__CPU_INORDER_USE_DEF_UNIT_HH__