src/cpu/inorder/resources/use_def.hh

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #ifndef __CPU_INORDER_USE_DEF_UNIT_HH__
  33 #define __CPU_INORDER_USE_DEF_UNIT_HH__
  34
  35 #include <list>
  36 #include <string>
  37 #include <vector>
  38
  39 #include "cpu/inorder/first_stage.hh"
  40 #include "cpu/inorder/inorder_dyn_inst.hh"
  41 #include "cpu/inorder/pipeline_traits.hh"
  42 #include "cpu/inorder/reg_dep_map.hh"
  43 #include "cpu/inorder/resource.hh"
  44 #include "cpu/func_unit.hh"
  45
  46 class UseDefUnit : public Resource {
  47   public:
  48     typedef ThePipeline::DynInstPtr DynInstPtr;
  49     typedef TheISA::RegIndex RegIndex;
  50
  51     enum Command {
  52         ReadSrcReg,
  53         WriteDestReg,
  54         MarkDestRegs
  55     };
  56
  57   public:
  58     UseDefUnit(std::string res_name, int res_id, int res_width,
  59                Cycles res_latency, InOrderCPU *_cpu,
  60                ThePipeline::Params *params);
  61
  62     void init();
  63
  64     ResourceRequest* getRequest(DynInstPtr _inst, int stage_num,
  65                                         int res_idx, int slot_num,
  66                                         unsigned cmd);
  67
  68     ResReqPtr findRequest(DynInstPtr inst);
  69
  70     void execute(int slot_num);
  71
  72     void updateAfterContextSwitch(DynInstPtr inst, ThreadID tid);
  73
  74     void regStats();
  75
  76   protected:
  77     RegDepMap *regDepMap[ThePipeline::MaxThreads];
  78
  79     bool *nonSpecInstActive[ThePipeline::MaxThreads];
  80     InstSeqNum *nonSpecSeqNum[ThePipeline::MaxThreads];
  81
  82     bool serializeOnNextInst[ThePipeline::MaxThreads];
  83     InstSeqNum serializeAfterSeqNum[ThePipeline::MaxThreads];
  84
  85     Stats::Average uniqueRegsPerSwitch;
  86     std::map<RegIndex, bool> uniqueIntRegMap;
  87     std::map<RegIndex, bool> uniqueFloatRegMap;
  88     std::map<RegIndex, bool> uniqueMiscRegMap;
  89
  90   public:
  91     class UseDefRequest : public ResourceRequest {
  92       public:
  93         typedef ThePipeline::DynInstPtr DynInstPtr;
  94
  95       public:
  96         UseDefRequest(UseDefUnit *res)
  97             : ResourceRequest(res)
  98         { }
  99
 100         int useDefIdx;
 101
 102         void setRequest(DynInstPtr _inst, int stage_num, int res_idx,
 103                         int slot_num, unsigned _cmd, int idx)
 104         {
 105             useDefIdx = idx;
 106
 107             ResourceRequest::setRequest(_inst, stage_num, res_idx, slot_num,
 108                                         _cmd);
 109         }
 110     };
 111
 112   protected:
 113     /** Int. Register File Reads */
 114     Stats::Scalar intRegFileReads;
 115
 116     /** Int. Register File Writes */
 117     Stats::Scalar intRegFileWrites;
 118
 119     /** Int. Register File Total Accesses (Read+Write) */
 120     Stats::Formula intRegFileAccs;
 121
 122     /** Float Register File Reads */
 123     Stats::Scalar floatRegFileReads;
 124
 125     /** Float Register File Writes */
 126     Stats::Scalar floatRegFileWrites;
 127
 128     /** Float Register File Total Accesses (Read+Write) */
 129     Stats::Formula floatRegFileAccs;
 130
 131     /** Source Register Forwarding */
 132     Stats::Scalar regForwards;
 133 };
 134
 135 #endif //__CPU_INORDER_USE_DEF_UNIT_HH__