2 * Copyright (c) 2007 MIPS Technologies, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Korey Sewell
32 #ifndef __CPU_INORDER_USE_DEF_UNIT_HH__
33 #define __CPU_INORDER_USE_DEF_UNIT_HH__
39 #include "cpu/inorder/first_stage.hh"
40 #include "cpu/inorder/inorder_dyn_inst.hh"
41 #include "cpu/inorder/pipeline_traits.hh"
42 #include "cpu/inorder/reg_dep_map.hh"
43 #include "cpu/inorder/resource.hh"
44 #include "cpu/func_unit.hh"
46 class UseDefUnit : public Resource {
48 typedef ThePipeline::DynInstPtr DynInstPtr;
56 UseDefUnit(std::string res_name, int res_id, int res_width,
57 int res_latency, InOrderCPU *_cpu, ThePipeline::Params *params);
61 ResourceRequest* getRequest(DynInstPtr _inst, int stage_num,
62 int res_idx, int slot_num,
65 ResReqPtr findRequest(DynInstPtr inst);
67 void execute(int slot_num);
69 void squash(DynInstPtr inst, int stage_num,
70 InstSeqNum squash_seq_num, ThreadID tid);
72 void updateAfterContextSwitch(DynInstPtr inst, ThreadID tid);
74 const InstSeqNum maxSeqNum;
79 RegDepMap *regDepMap[ThePipeline::MaxThreads];
81 /** Outstanding Seq. Num. Trying to Read from Register File */
82 InstSeqNum outReadSeqNum[ThePipeline::MaxThreads];
84 InstSeqNum outWriteSeqNum[ThePipeline::MaxThreads];
86 bool *nonSpecInstActive[ThePipeline::MaxThreads];
88 InstSeqNum *nonSpecSeqNum[ThePipeline::MaxThreads];
90 InstSeqNum floatRegSize[ThePipeline::MaxThreads];
92 Stats::Average uniqueRegsPerSwitch;
93 std::map<unsigned, bool> uniqueRegMap;
96 class UseDefRequest : public ResourceRequest {
98 typedef ThePipeline::DynInstPtr DynInstPtr;
101 UseDefRequest(UseDefUnit *res)
102 : ResourceRequest(res)
107 void setRequest(DynInstPtr _inst, int stage_num, int res_idx,
108 int slot_num, unsigned _cmd, int idx)
112 ResourceRequest::setRequest(_inst, stage_num, res_idx, slot_num,
118 /** Register File Reads */
119 Stats::Scalar regFileReads;
121 /** Register File Writes */
122 Stats::Scalar regFileWrites;
124 /** Source Register Forwarding */
125 Stats::Scalar regForwards;
127 /** Register File Total Accesses (Read+Write) */
128 Stats::Formula regFileAccs;
131 #endif //__CPU_INORDER_USE_DEF_UNIT_HH__