2 * Copyright (c) 2007 MIPS Technologies, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Korey Sewell
32 #include "arch/isa_traits.hh"
33 #include "config/the_isa.hh"
34 #include "cpu/inorder/thread_context.hh"
35 #include "cpu/exetrace.hh"
36 #include "debug/InOrderCPU.hh"
37 #include "sim/full_system.hh"
39 using namespace TheISA
;
41 FSTranslatingPortProxy
&
42 InOrderThreadContext::getVirtProxy()
44 return thread
->getVirtProxy();
48 InOrderThreadContext::dumpFuncProfile()
50 thread
->dumpFuncProfile();
55 InOrderThreadContext::readLastActivate()
57 return thread
->lastActivate
;
62 InOrderThreadContext::readLastSuspend()
64 return thread
->lastSuspend
;
69 InOrderThreadContext::profileClear()
71 thread
->profileClear();
76 InOrderThreadContext::profileSample()
78 thread
->profileSample();
82 InOrderThreadContext::takeOverFrom(ThreadContext
*old_context
)
84 // some things should already be set up
85 assert(getSystemPtr() == old_context
->getSystemPtr());
86 assert(getProcessPtr() == old_context
->getProcessPtr());
88 // copy over functional state
89 setStatus(old_context
->status());
90 copyArchRegs(old_context
);
92 thread
->funcExeInst
= old_context
->readFuncExeInst();
94 old_context
->setStatus(ThreadContext::Halted
);
96 thread
->inSyscall
= false;
97 thread
->trapPending
= false;
101 InOrderThreadContext::activate(int delay
)
103 DPRINTF(InOrderCPU
, "Calling activate on Thread Context %d\n",
106 if (thread
->status() == ThreadContext::Active
)
109 thread
->setStatus(ThreadContext::Active
);
111 cpu
->activateContext(thread
->threadId(), delay
);
116 InOrderThreadContext::suspend(int delay
)
118 DPRINTF(InOrderCPU
, "Calling suspend on Thread Context %d\n",
121 if (thread
->status() == ThreadContext::Suspended
)
124 thread
->setStatus(ThreadContext::Suspended
);
125 cpu
->suspendContext(thread
->threadId());
129 InOrderThreadContext::halt(int delay
)
131 DPRINTF(InOrderCPU
, "Calling halt on Thread Context %d\n",
134 if (thread
->status() == ThreadContext::Halted
)
137 thread
->setStatus(ThreadContext::Halted
);
138 cpu
->haltContext(thread
->threadId());
143 InOrderThreadContext::regStats(const std::string
&name
)
146 thread
->kernelStats
= new TheISA::Kernel::Statistics(cpu
->system
);
147 thread
->kernelStats
->regStats(name
+ ".kern");
153 InOrderThreadContext::serialize(std::ostream
&os
)
155 panic("serialize unimplemented");
160 InOrderThreadContext::unserialize(Checkpoint
*cp
, const std::string
§ion
)
162 panic("unserialize unimplemented");
167 InOrderThreadContext::copyArchRegs(ThreadContext
*src_tc
)
169 TheISA::copyRegs(src_tc
, this);
174 InOrderThreadContext::clearArchRegs()
176 cpu
->isa
[thread
->threadId()].clear();
181 InOrderThreadContext::readIntReg(int reg_idx
)
183 ThreadID tid
= thread
->threadId();
184 reg_idx
= cpu
->isa
[tid
].flattenIntIndex(reg_idx
);
185 return cpu
->readIntReg(reg_idx
, tid
);
189 InOrderThreadContext::readFloatReg(int reg_idx
)
191 ThreadID tid
= thread
->threadId();
192 reg_idx
= cpu
->isa
[tid
].flattenFloatIndex(reg_idx
);
193 return cpu
->readFloatReg(reg_idx
, tid
);
197 InOrderThreadContext::readFloatRegBits(int reg_idx
)
199 ThreadID tid
= thread
->threadId();
200 reg_idx
= cpu
->isa
[tid
].flattenFloatIndex(reg_idx
);
201 return cpu
->readFloatRegBits(reg_idx
, tid
);
205 InOrderThreadContext::readRegOtherThread(int reg_idx
, ThreadID tid
)
207 return cpu
->readRegOtherThread(reg_idx
, tid
);
211 InOrderThreadContext::setIntReg(int reg_idx
, uint64_t val
)
213 ThreadID tid
= thread
->threadId();
214 reg_idx
= cpu
->isa
[tid
].flattenIntIndex(reg_idx
);
215 cpu
->setIntReg(reg_idx
, val
, tid
);
219 InOrderThreadContext::setFloatReg(int reg_idx
, FloatReg val
)
221 ThreadID tid
= thread
->threadId();
222 reg_idx
= cpu
->isa
[tid
].flattenFloatIndex(reg_idx
);
223 cpu
->setFloatReg(reg_idx
, val
, tid
);
227 InOrderThreadContext::setFloatRegBits(int reg_idx
, FloatRegBits val
)
229 ThreadID tid
= thread
->threadId();
230 reg_idx
= cpu
->isa
[tid
].flattenFloatIndex(reg_idx
);
231 cpu
->setFloatRegBits(reg_idx
, val
, tid
);
235 InOrderThreadContext::setRegOtherThread(int misc_reg
, const MiscReg
&val
,
238 cpu
->setRegOtherThread(misc_reg
, val
, tid
);
242 InOrderThreadContext::setMiscRegNoEffect(int misc_reg
, const MiscReg
&val
)
244 cpu
->setMiscRegNoEffect(misc_reg
, val
, thread
->threadId());
248 InOrderThreadContext::setMiscReg(int misc_reg
, const MiscReg
&val
)
250 cpu
->setMiscReg(misc_reg
, val
, thread
->threadId());