src/cpu/inorder/thread_context.cc

   1 /*
   2  * Copyright (c) 2007 MIPS Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Korey Sewell
  29  *
  30  */
  31
  32 #include "arch/isa_traits.hh"
  33 #include "config/the_isa.hh"
  34 #include "cpu/inorder/thread_context.hh"
  35 #include "cpu/exetrace.hh"
  36 #include "debug/InOrderCPU.hh"
  37 #include "sim/full_system.hh"
  38
  39 using namespace TheISA;
  40
  41 FSTranslatingPortProxy&
  42 InOrderThreadContext::getVirtProxy()
  43 {
  44     return thread->getVirtProxy();
  45 }
  46
  47 void
  48 InOrderThreadContext::dumpFuncProfile()
  49 {
  50     thread->dumpFuncProfile();
  51 }
  52
  53
  54 Tick
  55 InOrderThreadContext::readLastActivate()
  56 {
  57     return thread->lastActivate;
  58 }
  59
  60
  61 Tick
  62 InOrderThreadContext::readLastSuspend()
  63 {
  64     return thread->lastSuspend;
  65 }
  66
  67
  68 void
  69 InOrderThreadContext::profileClear()
  70 {
  71     thread->profileClear();
  72 }
  73
  74
  75 void
  76 InOrderThreadContext::profileSample()
  77 {
  78     thread->profileSample();
  79 }
  80
  81 void
  82 InOrderThreadContext::takeOverFrom(ThreadContext *old_context)
  83 {
  84     // some things should already be set up
  85     assert(getSystemPtr() == old_context->getSystemPtr());
  86     assert(getProcessPtr() == old_context->getProcessPtr());
  87
  88     // copy over functional state
  89     setStatus(old_context->status());
  90     copyArchRegs(old_context);
  91
  92     thread->funcExeInst = old_context->readFuncExeInst();
  93
  94     old_context->setStatus(ThreadContext::Halted);
  95
  96     thread->inSyscall = false;
  97     thread->trapPending = false;
  98 }
  99
 100 void
 101 InOrderThreadContext::activate(int delay)
 102 {
 103     DPRINTF(InOrderCPU, "Calling activate on Thread Context %d\n",
 104             getThreadNum());
 105
 106     if (thread->status() == ThreadContext::Active)
 107         return;
 108
 109     thread->setStatus(ThreadContext::Active);
 110
 111     cpu->activateContext(thread->threadId(), delay);
 112 }
 113
 114
 115 void
 116 InOrderThreadContext::suspend(int delay)
 117 {
 118     DPRINTF(InOrderCPU, "Calling suspend on Thread Context %d\n",
 119             getThreadNum());
 120
 121     if (thread->status() == ThreadContext::Suspended)
 122         return;
 123
 124     thread->setStatus(ThreadContext::Suspended);
 125     cpu->suspendContext(thread->threadId());
 126 }
 127
 128 void
 129 InOrderThreadContext::halt(int delay)
 130 {
 131     DPRINTF(InOrderCPU, "Calling halt on Thread Context %d\n",
 132             getThreadNum());
 133
 134     if (thread->status() == ThreadContext::Halted)
 135         return;
 136
 137     thread->setStatus(ThreadContext::Halted);
 138     cpu->haltContext(thread->threadId());
 139 }
 140
 141
 142 void
 143 InOrderThreadContext::regStats(const std::string &name)
 144 {
 145     if (FullSystem) {
 146         thread->kernelStats = new TheISA::Kernel::Statistics(cpu->system);
 147         thread->kernelStats->regStats(name + ".kern");
 148     }
 149 }
 150
 151
 152 void
 153 InOrderThreadContext::serialize(std::ostream &os)
 154 {
 155     panic("serialize unimplemented");
 156 }
 157
 158
 159 void
 160 InOrderThreadContext::unserialize(Checkpoint *cp, const std::string &section)
 161 {
 162     panic("unserialize unimplemented");
 163 }
 164
 165
 166 void
 167 InOrderThreadContext::copyArchRegs(ThreadContext *src_tc)
 168 {
 169     TheISA::copyRegs(src_tc, this);
 170 }
 171
 172
 173 void
 174 InOrderThreadContext::clearArchRegs()
 175 {
 176     cpu->isa[thread->threadId()].clear();
 177 }
 178
 179
 180 uint64_t
 181 InOrderThreadContext::readIntReg(int reg_idx)
 182 {
 183     ThreadID tid = thread->threadId();
 184     reg_idx = cpu->isa[tid].flattenIntIndex(reg_idx);
 185     return cpu->readIntReg(reg_idx, tid);
 186 }
 187
 188 FloatReg
 189 InOrderThreadContext::readFloatReg(int reg_idx)
 190 {
 191     ThreadID tid = thread->threadId();
 192     reg_idx = cpu->isa[tid].flattenFloatIndex(reg_idx);
 193     return cpu->readFloatReg(reg_idx, tid);
 194 }
 195
 196 FloatRegBits
 197 InOrderThreadContext::readFloatRegBits(int reg_idx)
 198 {
 199     ThreadID tid = thread->threadId();
 200     reg_idx = cpu->isa[tid].flattenFloatIndex(reg_idx);
 201     return cpu->readFloatRegBits(reg_idx, tid);
 202 }
 203
 204 uint64_t
 205 InOrderThreadContext::readRegOtherThread(int reg_idx, ThreadID tid)
 206 {
 207     return cpu->readRegOtherThread(reg_idx, tid);
 208 }
 209
 210 void
 211 InOrderThreadContext::setIntReg(int reg_idx, uint64_t val)
 212 {
 213     ThreadID tid = thread->threadId();
 214     reg_idx = cpu->isa[tid].flattenIntIndex(reg_idx);
 215     cpu->setIntReg(reg_idx, val, tid);
 216 }
 217
 218 void
 219 InOrderThreadContext::setFloatReg(int reg_idx, FloatReg val)
 220 {
 221     ThreadID tid = thread->threadId();
 222     reg_idx = cpu->isa[tid].flattenFloatIndex(reg_idx);
 223     cpu->setFloatReg(reg_idx, val, tid);
 224 }
 225
 226 void
 227 InOrderThreadContext::setFloatRegBits(int reg_idx, FloatRegBits val)
 228 {
 229     ThreadID tid = thread->threadId();
 230     reg_idx = cpu->isa[tid].flattenFloatIndex(reg_idx);
 231     cpu->setFloatRegBits(reg_idx, val, tid);
 232 }
 233
 234 void
 235 InOrderThreadContext::setRegOtherThread(int misc_reg, const MiscReg &val,
 236                                         ThreadID tid)
 237 {
 238     cpu->setRegOtherThread(misc_reg, val, tid);
 239 }
 240
 241 void
 242 InOrderThreadContext::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
 243 {
 244     cpu->setMiscRegNoEffect(misc_reg, val, thread->threadId());
 245 }
 246
 247 void
 248 InOrderThreadContext::setMiscReg(int misc_reg, const MiscReg &val)
 249 {
 250     cpu->setMiscReg(misc_reg, val, thread->threadId());
 251 }