2 * Copyright (c) 2012 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 2007 MIPS Technologies, Inc.
15 * All rights reserved.
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 * Authors: Korey Sewell
44 #include "arch/isa_traits.hh"
45 #include "config/the_isa.hh"
46 #include "cpu/inorder/thread_context.hh"
47 #include "cpu/exetrace.hh"
48 #include "debug/InOrderCPU.hh"
49 #include "sim/full_system.hh"
51 using namespace TheISA
;
53 FSTranslatingPortProxy
&
54 InOrderThreadContext::getVirtProxy()
56 return thread
->getVirtProxy();
60 InOrderThreadContext::dumpFuncProfile()
62 thread
->dumpFuncProfile();
67 InOrderThreadContext::readLastActivate()
69 return thread
->lastActivate
;
74 InOrderThreadContext::readLastSuspend()
76 return thread
->lastSuspend
;
81 InOrderThreadContext::profileClear()
83 thread
->profileClear();
88 InOrderThreadContext::profileSample()
90 thread
->profileSample();
94 InOrderThreadContext::takeOverFrom(ThreadContext
*old_context
)
96 ::takeOverFrom(*this, *old_context
);
98 thread
->funcExeInst
= old_context
->readFuncExeInst();
100 thread
->noSquashFromTC
= false;
101 thread
->trapPending
= false;
105 InOrderThreadContext::activate(Cycles delay
)
107 DPRINTF(InOrderCPU
, "Calling activate on Thread Context %d\n",
110 if (thread
->status() == ThreadContext::Active
)
113 thread
->setStatus(ThreadContext::Active
);
115 cpu
->activateContext(thread
->threadId(), delay
);
120 InOrderThreadContext::suspend(Cycles delay
)
122 DPRINTF(InOrderCPU
, "Calling suspend on Thread Context %d\n",
125 if (thread
->status() == ThreadContext::Suspended
)
128 thread
->setStatus(ThreadContext::Suspended
);
129 cpu
->suspendContext(thread
->threadId());
133 InOrderThreadContext::halt(Cycles delay
)
135 DPRINTF(InOrderCPU
, "Calling halt on Thread Context %d\n",
138 if (thread
->status() == ThreadContext::Halted
)
141 thread
->setStatus(ThreadContext::Halted
);
142 cpu
->haltContext(thread
->threadId());
147 InOrderThreadContext::regStats(const std::string
&name
)
150 thread
->kernelStats
= new TheISA::Kernel::Statistics(cpu
->system
);
151 thread
->kernelStats
->regStats(name
+ ".kern");
156 InOrderThreadContext::copyArchRegs(ThreadContext
*src_tc
)
158 TheISA::copyRegs(src_tc
, this);
163 InOrderThreadContext::clearArchRegs()
165 cpu
->isa
[thread
->threadId()]->clear();
170 InOrderThreadContext::readIntReg(int reg_idx
)
172 ThreadID tid
= thread
->threadId();
173 reg_idx
= cpu
->isa
[tid
]->flattenIntIndex(reg_idx
);
174 return cpu
->readIntReg(reg_idx
, tid
);
178 InOrderThreadContext::readFloatReg(int reg_idx
)
180 ThreadID tid
= thread
->threadId();
181 reg_idx
= cpu
->isa
[tid
]->flattenFloatIndex(reg_idx
);
182 return cpu
->readFloatReg(reg_idx
, tid
);
186 InOrderThreadContext::readFloatRegBits(int reg_idx
)
188 ThreadID tid
= thread
->threadId();
189 reg_idx
= cpu
->isa
[tid
]->flattenFloatIndex(reg_idx
);
190 return cpu
->readFloatRegBits(reg_idx
, tid
);
194 InOrderThreadContext::readRegOtherThread(int reg_idx
, ThreadID tid
)
196 return cpu
->readRegOtherThread(reg_idx
, tid
);
200 InOrderThreadContext::setIntReg(int reg_idx
, uint64_t val
)
202 ThreadID tid
= thread
->threadId();
203 reg_idx
= cpu
->isa
[tid
]->flattenIntIndex(reg_idx
);
204 cpu
->setIntReg(reg_idx
, val
, tid
);
208 InOrderThreadContext::setFloatReg(int reg_idx
, FloatReg val
)
210 ThreadID tid
= thread
->threadId();
211 reg_idx
= cpu
->isa
[tid
]->flattenFloatIndex(reg_idx
);
212 cpu
->setFloatReg(reg_idx
, val
, tid
);
216 InOrderThreadContext::setFloatRegBits(int reg_idx
, FloatRegBits val
)
218 ThreadID tid
= thread
->threadId();
219 reg_idx
= cpu
->isa
[tid
]->flattenFloatIndex(reg_idx
);
220 cpu
->setFloatRegBits(reg_idx
, val
, tid
);
224 InOrderThreadContext::setRegOtherThread(int misc_reg
, const MiscReg
&val
,
227 cpu
->setRegOtherThread(misc_reg
, val
, tid
);
231 InOrderThreadContext::setMiscRegNoEffect(int misc_reg
, const MiscReg
&val
)
233 cpu
->setMiscRegNoEffect(misc_reg
, val
, thread
->threadId());
237 InOrderThreadContext::setMiscReg(int misc_reg
, const MiscReg
&val
)
239 cpu
->setMiscReg(misc_reg
, val
, thread
->threadId());
244 InOrderThreadContext::readIntRegFlat(int idx
)
246 const ThreadID tid
= thread
->threadId();
247 return cpu
->readIntReg(idx
, tid
);
251 InOrderThreadContext::setIntRegFlat(int idx
, uint64_t val
)
253 const ThreadID tid
= thread
->threadId();
254 cpu
->setIntReg(idx
, val
, tid
);
258 InOrderThreadContext::readFloatRegFlat(int idx
)
260 const ThreadID tid
= thread
->threadId();
261 return cpu
->readFloatReg(idx
, tid
);
265 InOrderThreadContext::setFloatRegFlat(int idx
, FloatReg val
)
267 const ThreadID tid
= thread
->threadId();
268 cpu
->setFloatReg(idx
, val
, tid
);
272 InOrderThreadContext::readFloatRegBitsFlat(int idx
)
274 const ThreadID tid
= thread
->threadId();
275 return cpu
->readFloatRegBits(idx
, tid
);
279 InOrderThreadContext::setFloatRegBitsFlat(int idx
, FloatRegBits val
)
281 const ThreadID tid
= thread
->threadId();
282 cpu
->setFloatRegBits(idx
, val
, tid
);