2 * Copyright (c) 2007 MIPS Technologies, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Korey Sewell
32 #ifndef __CPU_INORDER_THREAD_CONTEXT_HH__
33 #define __CPU_INORDER_THREAD_CONTEXT_HH__
35 #include "config/the_isa.hh"
36 #include "cpu/inorder/cpu.hh"
37 #include "cpu/inorder/thread_state.hh"
38 #include "cpu/exetrace.hh"
39 #include "cpu/thread_context.hh"
40 #include "arch/kernel_stats.hh"
42 class EndQuiesceEvent;
47 class TranslatingPort;
50 * Derived ThreadContext class for use with the InOrderCPU. It
51 * provides the interface for any external objects to access a
52 * single thread's state and some general CPU state. Any time
53 * external objects try to update state through this interface,
54 * the CPU will create an event to squash all in-flight
55 * instructions in order to ensure state is maintained correctly.
56 * It must be defined specifically for the InOrderCPU because
57 * not all architectural state is located within the O3ThreadState
58 * (such as the commit PC, and registers), and specific actions
59 * must be taken when using this interface (such as squashing all
60 * in-flight instructions when doing a write to this interface).
62 class InOrderThreadContext : public ThreadContext
65 InOrderThreadContext() { }
67 /** Pointer to the CPU. */
70 /** Pointer to the thread state that this TC corrseponds to. */
71 InOrderThreadState *thread;
73 /** Returns a pointer to the ITB. */
74 /** @TODO: PERF: Should we bind this to a pointer in constructor? */
75 TheISA::TLB *getITBPtr() { return cpu->getITBPtr(); }
77 /** Returns a pointer to the DTB. */
78 /** @TODO: PERF: Should we bind this to a pointer in constructor? */
79 TheISA::TLB *getDTBPtr() { return cpu->getDTBPtr(); }
81 System *getSystemPtr() { return cpu->system; }
83 /** Returns a pointer to this CPU. */
84 BaseCPU *getCpuPtr() { return cpu; }
86 /** Returns a pointer to this CPU. */
87 std::string getCpuName() { return cpu->name(); }
89 /** Reads this CPU's ID. */
90 int cpuId() { return cpu->cpuId(); }
92 int contextId() { return thread->contextId(); }
94 void setContextId(int id) { thread->setContextId(id); }
96 /** Returns this thread's ID number. */
97 int threadId() { return thread->threadId(); }
98 void setThreadId(int id) { return thread->setThreadId(id); }
100 uint64_t readMicroPC()
103 void setMicroPC(uint64_t val) { };
105 uint64_t readNextMicroPC()
108 void setNextMicroPC(uint64_t val) { };
111 /** Returns a pointer to physical memory. */
112 PhysicalMemory *getPhysMemPtr()
113 { assert(0); return 0; /*return cpu->physmem;*/ }
115 /** Returns a pointer to this thread's kernel statistics. */
116 TheISA::Kernel::Statistics *getKernelStats()
117 { return thread->kernelStats; }
119 FunctionalPort *getPhysPort() { return thread->getPhysPort(); }
121 VirtualPort *getVirtPort();
123 void connectMemPorts(ThreadContext *tc)
124 { thread->connectMemPorts(tc); }
126 /** Dumps the function profiling information.
129 void dumpFuncProfile();
131 /** Reads the last tick that this thread was activated on. */
132 Tick readLastActivate();
133 /** Reads the last tick that this thread was suspended on. */
134 Tick readLastSuspend();
136 /** Clears the function profiling information. */
139 /** Samples the function profiling information. */
140 void profileSample();
142 /** Returns pointer to the quiesce event. */
143 EndQuiesceEvent *getQuiesceEvent()
145 return this->thread->quiesceEvent;
148 TranslatingPort *getMemPort() { return thread->getMemPort(); }
150 /** Returns a pointer to this thread's process. */
151 Process *getProcessPtr() { return thread->getProcessPtr(); }
154 /** Returns this thread's status. */
155 Status status() const { return thread->status(); }
157 /** Sets this thread's status. */
158 void setStatus(Status new_status)
159 { thread->setStatus(new_status); }
161 /** Set the status to Active. Optional delay indicates number of
162 * cycles to wait before beginning execution. */
163 void activate(int delay = 1);
165 /** Set the status to Suspended. */
166 void suspend(int delay = 0);
168 /** Set the status to Halted. */
169 void halt(int delay = 0);
171 /** Takes over execution of a thread from another CPU. */
172 void takeOverFrom(ThreadContext *old_context);
174 /** Registers statistics associated with this TC. */
175 void regStats(const std::string &name);
177 /** Serializes state. */
178 void serialize(std::ostream &os);
180 /** Unserializes state. */
181 void unserialize(Checkpoint *cp, const std::string §ion);
183 /** Returns this thread's ID number. */
184 int getThreadNum() { return thread->threadId(); }
186 /** Copies the architectural registers from another TC into this TC. */
187 void copyArchRegs(ThreadContext *src_tc);
189 /** Resets all architectural registers to 0. */
190 void clearArchRegs();
192 /** Reads an integer register. */
193 uint64_t readIntReg(int reg_idx);
195 FloatReg readFloatReg(int reg_idx);
197 FloatRegBits readFloatRegBits(int reg_idx);
199 uint64_t readRegOtherThread(int misc_reg, ThreadID tid);
201 /** Sets an integer register to a value. */
202 void setIntReg(int reg_idx, uint64_t val);
204 void setFloatReg(int reg_idx, FloatReg val);
206 void setFloatRegBits(int reg_idx, FloatRegBits val);
208 void setRegOtherThread(int misc_reg,
212 /** Reads this thread's PC. */
213 TheISA::PCState pcState()
214 { return cpu->pcState(thread->threadId()); }
216 /** Sets this thread's PC. */
217 void pcState(const TheISA::PCState &val)
218 { cpu->pcState(val, thread->threadId()); }
221 { return cpu->instAddr(thread->threadId()); }
224 { return cpu->nextInstAddr(thread->threadId()); }
227 { return cpu->microPC(thread->threadId()); }
229 /** Reads a miscellaneous register. */
230 MiscReg readMiscRegNoEffect(int misc_reg)
231 { return cpu->readMiscRegNoEffect(misc_reg, thread->threadId()); }
233 /** Reads a misc. register, including any side-effects the
234 * read might have as defined by the architecture. */
235 MiscReg readMiscReg(int misc_reg)
236 { return cpu->readMiscReg(misc_reg, thread->threadId()); }
238 /** Sets a misc. register. */
239 void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
241 /** Sets a misc. register, including any side-effects the
242 * write might have as defined by the architecture. */
243 void setMiscReg(int misc_reg, const MiscReg &val);
245 int flattenIntIndex(int reg)
246 { return cpu->isa[thread->threadId()].flattenIntIndex(reg); }
248 int flattenFloatIndex(int reg)
249 { return cpu->isa[thread->threadId()].flattenFloatIndex(reg); }
251 void activateContext(int delay)
252 { cpu->activateContext(thread->threadId(), delay); }
254 void deallocateContext()
255 { cpu->deallocateContext(thread->threadId()); }
257 /** Returns the number of consecutive store conditional failures. */
258 // @todo: Figure out where these store cond failures should go.
259 unsigned readStCondFailures()
260 { return thread->storeCondFailures; }
262 /** Sets the number of consecutive store conditional failures. */
263 void setStCondFailures(unsigned sc_failures)
264 { thread->storeCondFailures = sc_failures; }
266 // Only really makes sense for old CPU model. Lots of code
267 // outside the CPU still checks this function, so it will
268 // always return false to keep everything working.
269 /** Checks if the thread is misspeculating. Because it is
270 * very difficult to determine if the thread is
271 * misspeculating, this is set as false. */
272 bool misspeculating() { return false; }
275 /** Executes a syscall in SE mode. */
276 void syscall(int64_t callnum)
277 { return cpu->syscall(callnum, thread->threadId()); }
280 /** Reads the funcExeInst counter. */
281 Counter readFuncExeInst() { return thread->funcExeInst; }
283 void changeRegFileContext(unsigned param,
285 { panic("Not supported!"); }